Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	17657187	9252	0	0
EscTimeoutStoppedByClReset_A	17656601	2419585	0	0
EscTimeoutTriggersReset_A	4139112	434	0	0
RomAllowActiveState_A	17656601	45822	0	0
RomAllowCheckGoodState_A	17656601	45873	0	0
RomBlockActiveState_A	17656601	26917	0	0
RomBlockCheckGoodState_A	17656601	358437	0	0
RomIntgChkDisFalse_A	17656601	17086814	0	0
RomIntgChkDisTrue_A	17656601	143174	0	0
RstreqChkEsctimeout_A	17656601	3287	0	0
RstreqChkFsmterm_A	17656601	100	0	0
RstreqChkGlbesc_A	17656601	3287	0	0
RstreqChkMainpd_A	17656601	697190	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17657187	9252	0	0
T9	2439	34	0	0
T10	6649	0	0	0
T11	10457	287	0	0
T13	1461	0	0	0
T14	5797	0	0	0
T17	2998	0	0	0
T20	8969	0	0	0
T28	3126	0	0	0
T37	56331	0	0	0
T40	1762	0	0	0
T89	0	9	0	0
T109	0	16	0	0
T111	0	202	0	0
T151	0	176	0	0
T152	0	209	0	0
T153	0	86	0	0
T154	0	29	0	0
T155	0	124	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	2419585	0	0
T1	1464	20	0	0
T2	2665	401	0	0
T3	3830	622	0	0
T4	17065	3429	0	0
T5	1710	115	0	0
T6	3250	4	0	0
T7	6948	47	0	0
T8	16691	3193	0	0
T9	2438	66	0	0
T10	6648	417	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4139112	434	0	0
T9	210	3	0	0
T10	1054	0	0	0
T11	148	4	0	0
T12	0	3	0	0
T13	492	0	0	0
T14	430	0	0	0
T17	279	0	0	0
T20	3288	0	0	0
T28	1035	0	0	0
T37	5893	0	0	0
T40	577	0	0	0
T89	0	4	0	0
T109	0	2	0	0
T111	0	5	0	0
T151	0	5	0	0
T152	0	4	0	0
T153	0	6	0	0
T156	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	45822	0	0
T1	1464	3	0	0
T2	2665	23	0	0
T3	3830	20	0	0
T4	17065	19	0	0
T5	1710	5	0	0
T6	3250	11	0	0
T7	6948	5	0	0
T8	16691	85	0	0
T9	2438	3	0	0
T10	6648	11	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	45873	0	0
T1	1464	3	0	0
T2	2665	23	0	0
T3	3830	20	0	0
T4	17065	19	0	0
T5	1710	5	0	0
T6	3250	11	0	0
T7	6948	5	0	0
T8	16691	85	0	0
T9	2438	3	0	0
T10	6648	11	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	26917	0	0
T14	5797	1439	0	0
T20	8968	0	0	0
T27	0	730	0	0
T28	3125	0	0	0
T31	1366	0	0	0
T32	4515	0	0	0
T33	9242	0	0	0
T34	4319	0	0	0
T35	18868	0	0	0
T37	56330	0	0	0
T40	1761	0	0	0
T44	0	4	0	0
T157	0	257	0	0
T158	0	688	0	0
T159	0	112	0	0
T160	0	30	0	0
T161	0	12	0	0
T162	0	215	0	0
T163	0	500	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	358437	0	0
T5	1710	46	0	0
T6	3250	0	0	0
T7	6948	0	0	0
T8	16691	1291	0	0
T9	2438	0	0	0
T10	6648	0	0	0
T11	10456	0	0	0
T13	1460	0	0	0
T14	5797	877	0	0
T16	0	871	0	0
T17	2997	0	0	0
T23	0	457	0	0
T26	0	4011	0	0
T27	0	411	0	0
T35	0	389	0	0
T37	0	4135	0	0
T145	0	2192	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	17086814	0	0
T1	1464	1374	0	0
T2	2665	2488	0	0
T3	3830	3749	0	0
T4	17065	16987	0	0
T5	1710	1652	0	0
T6	3250	3197	0	0
T7	6948	6867	0	0
T8	16691	16290	0	0
T9	2438	2328	0	0
T10	6648	6586	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	143174	0	0
T8	16691	312	0	0
T9	2438	0	0	0
T10	6648	0	0	0
T11	10456	0	0	0
T13	1460	0	0	0
T14	5797	1851	0	0
T17	2997	0	0	0
T26	0	1538	0	0
T27	0	1652	0	0
T28	3125	0	0	0
T37	56330	0	0	0
T40	1761	0	0	0
T110	0	924	0	0
T158	0	967	0	0
T159	0	811	0	0
T161	0	8458	0	0
T164	0	3091	0	0
T165	0	694	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	3287	0	0
T2	2665	9	0	0
T3	3830	0	0	0
T4	17065	0	0	0
T5	1710	0	0	0
T6	3250	0	0	0
T7	6948	0	0	0
T8	16691	0	0	0
T9	2438	1	0	0
T10	6648	0	0	0
T11	0	2	0	0
T13	1460	4	0	0
T14	0	3	0	0
T16	0	7	0	0
T20	0	10	0	0
T23	0	11	0	0
T28	0	5	0	0
T32	0	6	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	100	0	0
T15	3675	0	0	0
T16	22099	0	0	0
T20	8968	20	0	0
T21	0	20	0	0
T22	0	20	0	0
T23	43039	0	0	0
T29	0	20	0	0
T30	0	20	0	0
T31	1366	0	0	0
T32	4515	0	0	0
T33	9242	0	0	0
T34	4319	0	0	0
T35	18868	0	0	0
T36	4261	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	3287	0	0
T2	2665	9	0	0
T3	3830	0	0	0
T4	17065	0	0	0
T5	1710	0	0	0
T6	3250	0	0	0
T7	6948	0	0	0
T8	16691	0	0	0
T9	2438	1	0	0
T10	6648	0	0	0
T11	0	2	0	0
T13	1460	4	0	0
T14	0	3	0	0
T16	0	7	0	0
T20	0	10	0	0
T23	0	11	0	0
T28	0	5	0	0
T32	0	6	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	697190	0	0
T2	2665	219	0	0
T3	3830	0	0	0
T4	17065	0	0	0
T5	1710	90	0	0
T6	3250	0	0	0
T7	6948	0	0	0
T8	16691	1233	0	0
T9	2438	0	0	0
T10	6648	0	0	0
T13	1460	0	0	0
T14	0	2842	0	0
T16	0	915	0	0
T17	0	18	0	0
T28	0	114	0	0
T32	0	603	0	0
T35	0	658	0	0
T37	0	3755	0	0