RSTMGR Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	2.140s	249.738us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.810s	114.779us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.880s	62.745us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	8.890s	2.315ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.280s	400.369us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.890s	184.898us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.880s	62.745us	20	20	100.00
		rstmgr_csr_aliasing	2.280s	400.369us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.520s	224.482us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	3.150s	352.402us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.720s	191.578us	50	50	100.00
V2	reset_info	rstmgr_reset	8.590s	2.104ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.590s	2.104ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.590s	2.104ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.590s	2.104ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	54.220s	15.735ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	1.200s	81.907us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.180s	422.153us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.180s	422.153us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.810s	114.779us	5	5	100.00
		rstmgr_csr_rw	0.880s	62.745us	20	20	100.00
		rstmgr_csr_aliasing	2.280s	400.369us	5	5	100.00
		rstmgr_same_csr_outstanding	1.730s	196.817us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.810s	114.779us	5	5	100.00
		rstmgr_csr_rw	0.880s	62.745us	20	20	100.00
		rstmgr_csr_aliasing	2.280s	400.369us	5	5	100.00
		rstmgr_same_csr_outstanding	1.730s	196.817us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	35.250s	22.714ms	5	5	100.00
		rstmgr_tl_intg_err	4.720s	1.893ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	35.250s	22.714ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	35.250s	22.714ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	4.720s	1.893ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.810s	164.940us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.760s	2.455ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	2.210s	301.247us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	35.250s	22.714ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.880s	62.745us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.880s	62.745us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.46	99.40	99.31	100.00	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.08.26_02.23.26
• 2024.08.24_20.34.41
• 2024.08.22_14.36.36
• 2024.08.20_08.18.51
• 2024.08.19_08.32.01