RSTMGR Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.590s 255.152us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.120s 149.789us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.000s 83.286us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.350s 1.571ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.570s 471.825us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.820s 190.405us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.000s 83.286us 20 20 100.00
rstmgr_csr_aliasing 2.570s 471.825us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 44.516s 49 50 98.00
V2 sw_rst rstmgr_sw_rst 44.451s 49 50 98.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 44.472s 49 50 98.00
V2 reset_info rstmgr_reset 44.490s 49 50 98.00
V2 cpu_info rstmgr_reset 44.490s 49 50 98.00
V2 alert_info rstmgr_reset 44.490s 49 50 98.00
V2 reset_info_capture rstmgr_reset 44.490s 49 50 98.00
V2 stress_all rstmgr_stress_all 55.950s 16.510ms 49 50 98.00
V2 alert_test rstmgr_alert_test 44.282s 49 50 98.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.670s 542.874us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.670s 542.874us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.120s 149.789us 5 5 100.00
rstmgr_csr_rw 1.000s 83.286us 20 20 100.00
rstmgr_csr_aliasing 2.570s 471.825us 5 5 100.00
rstmgr_same_csr_outstanding 1.620s 217.914us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.120s 149.789us 5 5 100.00
rstmgr_csr_rw 1.000s 83.286us 20 20 100.00
rstmgr_csr_aliasing 2.570s 471.825us 5 5 100.00
rstmgr_same_csr_outstanding 1.620s 217.914us 20 20 100.00
V2 TOTAL 334 340 98.24
V2S tl_intg_err rstmgr_sec_cm 25.730s 16.515ms 5 5 100.00
rstmgr_tl_intg_err 3.250s 922.074us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 25.730s 16.515ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 25.730s 16.515ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.250s 922.074us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 44.418s 49 50 98.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.190s 2.440ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.660s 301.948us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 25.730s 16.515ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.000s 83.286us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.000s 83.286us 20 20 100.00
V2S TOTAL 174 175 99.43
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 613 620 98.87

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 2 25.00
V2S 5 5 4 80.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.45 99.40 99.24 100.00 -- 99.83 99.46 98.77

Failure Buckets

Past Results