RSTMGR Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 49.519s 47 50 94.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.890s 141.526us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.880s 84.030us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.300s 2.293ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.110s 344.819us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.730s 203.112us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.880s 84.030us 20 20 100.00
rstmgr_csr_aliasing 2.110s 344.819us 5 5 100.00
V1 TOTAL 102 105 97.14
V2 reset_stretcher rstmgr_por_stretcher 49.492s 48 50 96.00
V2 sw_rst rstmgr_sw_rst 49.416s 46 50 92.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 49.444s 46 50 92.00
V2 reset_info rstmgr_reset 49.470s 46 50 92.00
V2 cpu_info rstmgr_reset 49.470s 46 50 92.00
V2 alert_info rstmgr_reset 49.470s 46 50 92.00
V2 reset_info_capture rstmgr_reset 49.470s 46 50 92.00
V2 stress_all rstmgr_stress_all 53.720s 15.838ms 46 50 92.00
V2 alert_test rstmgr_alert_test 42.521s 47 50 94.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 25.211s 19 20 95.00
V2 tl_d_illegal_access rstmgr_tl_errors 25.211s 19 20 95.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.890s 141.526us 5 5 100.00
rstmgr_csr_rw 0.880s 84.030us 20 20 100.00
rstmgr_csr_aliasing 2.110s 344.819us 5 5 100.00
rstmgr_same_csr_outstanding 39.104s 19 20 95.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.890s 141.526us 5 5 100.00
rstmgr_csr_rw 0.880s 84.030us 20 20 100.00
rstmgr_csr_aliasing 2.110s 344.819us 5 5 100.00
rstmgr_same_csr_outstanding 39.104s 19 20 95.00
V2 TOTAL 317 340 93.24
V2S tl_intg_err rstmgr_sec_cm 29.240s 16.553ms 5 5 100.00
rstmgr_tl_intg_err 25.212s 18 20 90.00
V2S prim_count_check rstmgr_sec_cm 29.240s 16.553ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 29.240s 16.553ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 25.212s 18 20 90.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 49.390s 46 50 92.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 42.116s 48 50 96.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 39.437s 48 50 96.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 29.240s 16.553ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.880s 84.030us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.880s 84.030us 20 20 100.00
V2S TOTAL 165 175 94.29
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 584 620 94.19

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 8 8 0 0.00
V2S 5 5 1 20.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Failure Buckets

Past Results