RSTMGR Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 41.451s 49 50 98.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.430s 104.901us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.400s 81.953us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 7.640s 483.288us 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 3.160s 477.618us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.030s 178.693us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.400s 81.953us 20 20 100.00
rstmgr_csr_aliasing 3.160s 477.618us 5 5 100.00
V1 TOTAL 104 105 99.05
V2 reset_stretcher rstmgr_por_stretcher 41.569s 49 50 98.00
V2 sw_rst rstmgr_sw_rst 26.716s 49 50 98.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 26.587s 49 50 98.00
V2 reset_info rstmgr_reset 26.496s 49 50 98.00
V2 cpu_info rstmgr_reset 26.496s 49 50 98.00
V2 alert_info rstmgr_reset 26.496s 49 50 98.00
V2 reset_info_capture rstmgr_reset 26.496s 49 50 98.00
V2 stress_all rstmgr_stress_all 54.740s 15.806ms 49 50 98.00
V2 alert_test rstmgr_alert_test 41.330s 48 50 96.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.650s 659.068us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.650s 659.068us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.430s 104.901us 5 5 100.00
rstmgr_csr_rw 1.400s 81.953us 20 20 100.00
rstmgr_csr_aliasing 3.160s 477.618us 5 5 100.00
rstmgr_same_csr_outstanding 1.910s 282.782us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.430s 104.901us 5 5 100.00
rstmgr_csr_rw 1.400s 81.953us 20 20 100.00
rstmgr_csr_aliasing 3.160s 477.618us 5 5 100.00
rstmgr_same_csr_outstanding 1.910s 282.782us 20 20 100.00
V2 TOTAL 333 340 97.94
V2S tl_intg_err rstmgr_sec_cm 36.330s 16.524ms 5 5 100.00
rstmgr_tl_intg_err 4.950s 1.342ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 36.330s 16.524ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 36.330s 16.524ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 4.950s 1.342ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 41.145s 48 50 96.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 33.841s 49 50 98.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 41.241s 47 50 94.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 36.330s 16.524ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.400s 81.953us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.400s 81.953us 20 20 100.00
V2S TOTAL 169 175 96.57
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 606 620 97.74

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 8 8 2 25.00
V2S 5 5 2 40.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Failure Buckets

Past Results