RSTMGR Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 23.340s 49 50 98.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.290s 145.820us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.310s 87.148us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.910s 2.315ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.180s 236.036us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.760s 206.859us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.310s 87.148us 20 20 100.00
rstmgr_csr_aliasing 2.180s 236.036us 5 5 100.00
V1 TOTAL 104 105 99.05
V2 reset_stretcher rstmgr_por_stretcher 1.480s 153.151us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.170s 483.244us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 38.487s 49 50 98.00
V2 reset_info rstmgr_reset 8.450s 1.652ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.450s 1.652ms 50 50 100.00
V2 alert_info rstmgr_reset 8.450s 1.652ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.450s 1.652ms 50 50 100.00
V2 stress_all rstmgr_stress_all 55.310s 16.525ms 48 50 96.00
V2 alert_test rstmgr_alert_test 39.131s 48 50 96.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.230s 637.126us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.230s 637.126us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.290s 145.820us 5 5 100.00
rstmgr_csr_rw 1.310s 87.148us 20 20 100.00
rstmgr_csr_aliasing 2.180s 236.036us 5 5 100.00
rstmgr_same_csr_outstanding 2.420s 238.117us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.290s 145.820us 5 5 100.00
rstmgr_csr_rw 1.310s 87.148us 20 20 100.00
rstmgr_csr_aliasing 2.180s 236.036us 5 5 100.00
rstmgr_same_csr_outstanding 2.420s 238.117us 20 20 100.00
V2 TOTAL 335 340 98.53
V2S tl_intg_err rstmgr_sec_cm 30.820s 16.568ms 5 5 100.00
rstmgr_tl_intg_err 3.480s 874.615us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 30.820s 16.568ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 30.820s 16.568ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.480s 874.615us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 38.580s 48 50 96.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 38.725s 48 50 96.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 38.858s 49 50 98.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 30.820s 16.568ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.310s 87.148us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.310s 87.148us 20 20 100.00
V2S TOTAL 170 175 97.14
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 609 620 98.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 8 8 5 62.50
V2S 5 5 2 40.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Failure Buckets

Past Results