RSTMGR Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.730s 255.899us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.330s 99.951us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.370s 94.617us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.850s 1.998ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.260s 210.278us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.930s 193.775us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.370s 94.617us 20 20 100.00
rstmgr_csr_aliasing 2.260s 210.278us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.680s 224.324us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 4.630s 506.085us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.370s 251.694us 50 50 100.00
V2 reset_info rstmgr_reset 12.230s 1.803ms 50 50 100.00
V2 cpu_info rstmgr_reset 12.230s 1.803ms 50 50 100.00
V2 alert_info rstmgr_reset 12.230s 1.803ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 12.230s 1.803ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.033m 15.209ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.390s 88.365us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.780s 747.781us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.780s 747.781us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.330s 99.951us 5 5 100.00
rstmgr_csr_rw 1.370s 94.617us 20 20 100.00
rstmgr_csr_aliasing 2.260s 210.278us 5 5 100.00
rstmgr_same_csr_outstanding 2.250s 242.194us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.330s 99.951us 5 5 100.00
rstmgr_csr_rw 1.370s 94.617us 20 20 100.00
rstmgr_csr_aliasing 2.260s 210.278us 5 5 100.00
rstmgr_same_csr_outstanding 2.250s 242.194us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 35.720s 17.096ms 5 5 100.00
rstmgr_tl_intg_err 4.730s 778.491us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 35.720s 17.096ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 35.720s 17.096ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 4.730s 778.491us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 2.070s 178.034us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 14.080s 2.223ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 2.230s 301.069us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 35.720s 17.096ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.370s 94.617us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.370s 94.617us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Past Results