KEYMGR Simulation Results

Thursday February 22 2024 20:02:27 UTC

GitHub Revision: 952e4400c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3269902080

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 37.920s 2.957ms 50 50 100.00
V1 random keymgr_random 1.357m 27.976ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.560s 33.519us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.270s 18.112us 16 20 80.00
V1 csr_bit_bash keymgr_csr_bit_bash 23.520s 4.765ms 4 5 80.00
V1 csr_aliasing keymgr_csr_aliasing 13.820s 377.227us 3 5 60.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.010s 98.288us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.270s 18.112us 16 20 80.00
keymgr_csr_aliasing 13.820s 377.227us 3 5 60.00
V1 TOTAL 147 155 94.84
V2 cfgen_during_op keymgr_cfg_regwen 1.654m 7.764ms 49 50 98.00
V2 sideload keymgr_sideload 1.086m 3.650ms 50 50 100.00
keymgr_sideload_kmac 1.497m 6.917ms 50 50 100.00
keymgr_sideload_aes 1.528m 9.056ms 50 50 100.00
keymgr_sideload_otbn 1.385m 7.787ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.036m 16.286ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 13.160s 467.864us 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 57.420s 13.546ms 46 50 92.00
V2 invalid_sw_input keymgr_sw_invalid_input 36.260s 3.505ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.772m 11.052ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 34.130s 4.099ms 49 50 98.00
V2 stress_all keymgr_stress_all 7.930m 79.556ms 49 50 98.00
V2 intr_test keymgr_intr_test 0.870s 112.725us 50 50 100.00
V2 alert_test keymgr_alert_test 1.010s 42.204us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 5.420s 274.581us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 5.420s 274.581us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.560s 33.519us 5 5 100.00
keymgr_csr_rw 1.270s 18.112us 16 20 80.00
keymgr_csr_aliasing 13.820s 377.227us 3 5 60.00
keymgr_same_csr_outstanding 2.690s 323.261us 14 20 70.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.560s 33.519us 5 5 100.00
keymgr_csr_rw 1.270s 18.112us 16 20 80.00
keymgr_csr_aliasing 13.820s 377.227us 3 5 60.00
keymgr_same_csr_outstanding 2.690s 323.261us 14 20 70.00
V2 TOTAL 727 740 98.24
V2S sec_cm_additional_check keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
keymgr_tl_intg_err 1.304m 2.538ms 16 20 80.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 13.640s 681.596us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 13.640s 681.596us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 13.640s 681.596us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 13.640s 681.596us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 15.110s 1.606ms 10 20 50.00
V2S prim_count_check keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 1.304m 2.538ms 16 20 80.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 13.640s 681.596us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.654m 7.764ms 49 50 98.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.357m 27.976ms 50 50 100.00
keymgr_csr_rw 1.270s 18.112us 16 20 80.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.357m 27.976ms 50 50 100.00
keymgr_csr_rw 1.270s 18.112us 16 20 80.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.357m 27.976ms 50 50 100.00
keymgr_csr_rw 1.270s 18.112us 16 20 80.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 13.160s 467.864us 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.772m 11.052ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.772m 11.052ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.357m 27.976ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 17.530s 825.948us 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.216m 4.555ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 13.160s 467.864us 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.216m 4.555ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.216m 4.555ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.216m 4.555ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 44.860s 10.476ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.216m 4.555ms 50 50 100.00
V2S TOTAL 151 165 91.52
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 14.890s 1.156ms 43 50 86.00
V3 TOTAL 43 50 86.00
TOTAL 1068 1110 96.22

Testplan Progress

Items Total Written Passing Progress
V1 7 7 3 42.86
V2 16 16 11 68.75
V2S 6 6 4 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.83 99.10 97.91 98.64 100.00 99.11 98.41 91.61

Failure Buckets

Past Results