KEYMGR Simulation Results

Saturday March 02 2024 20:02:25 UTC

GitHub Revision: `2f1cc9b27a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2863389695

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	52.120s	7.540ms	50	50	100.00
V1	random	keymgr_random	1.348m	11.257ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.120s	33.273us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.160s	33.458us	16	20	80.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.140s	1.403ms	1	5	20.00
V1	csr_aliasing	keymgr_csr_aliasing	14.180s	360.449us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.920s	95.656us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.160s	33.458us	16	20	80.00
		keymgr_csr_aliasing	14.180s	360.449us	4	5	80.00
V1		TOTAL			146	155	94.19
V2	cfgen_during_op	keymgr_cfg_regwen	2.220m	10.538ms	50	50	100.00
V2	sideload	keymgr_sideload	54.490s	2.851ms	50	50	100.00
		keymgr_sideload_kmac	47.530s	1.959ms	50	50	100.00
		keymgr_sideload_aes	1.681m	8.728ms	50	50	100.00
		keymgr_sideload_otbn	49.520s	3.945ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	40.750s	1.755ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	31.030s	2.501ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.263m	10.981ms	44	50	88.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.593m	7.103ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.403m	8.684ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	27.050s	1.346ms	50	50	100.00
V2	stress_all	keymgr_stress_all	3.025m	26.788ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.900s	49.459us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.980s	14.050us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.470s	261.112us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.470s	261.112us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.120s	33.273us	5	5	100.00
		keymgr_csr_rw	1.160s	33.458us	16	20	80.00
		keymgr_csr_aliasing	14.180s	360.449us	4	5	80.00
		keymgr_same_csr_outstanding	3.750s	108.815us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.120s	33.273us	5	5	100.00
		keymgr_csr_rw	1.160s	33.458us	16	20	80.00
		keymgr_csr_aliasing	14.180s	360.449us	4	5	80.00
		keymgr_same_csr_outstanding	3.750s	108.815us	14	20	70.00
V2		TOTAL			725	740	97.97
V2S	sec_cm_additional_check	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
		keymgr_tl_intg_err	40.990s	5.986ms	12	20	60.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	18.120s	1.415ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	18.120s	1.415ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	18.120s	1.415ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	18.120s	1.415ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.740s	434.289us	14	20	70.00
V2S	prim_count_check	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	40.990s	5.986ms	12	20	60.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	18.120s	1.415ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.220m	10.538ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.348m	11.257ms	50	50	100.00
		keymgr_csr_rw	1.160s	33.458us	16	20	80.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.348m	11.257ms	50	50	100.00
		keymgr_csr_rw	1.160s	33.458us	16	20	80.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.348m	11.257ms	50	50	100.00
		keymgr_csr_rw	1.160s	33.458us	16	20	80.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	31.030s	2.501ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.403m	8.684ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.403m	8.684ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.348m	11.257ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	36.990s	3.952ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	41.020s	4.337ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	31.030s	2.501ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	41.020s	4.337ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	41.020s	4.337ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	41.020s	4.337ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	1.048m	2.924ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	41.020s	4.337ms	50	50	100.00
V2S		TOTAL			151	165	91.52
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	17.100s	305.720us	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			1067	1110	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	4	57.14
V2	16	16	12	75.00
V2S	6	6	4	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.86	99.10	97.95	98.68	100.00	99.11	98.41	91.76

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 29 failures:

Test keymgr_tl_intg_err has 8 failures.

0.keymgr_tl_intg_err.3893804055
Line 289, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @ 191928062 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @ 191928062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_tl_intg_err.1406292363
Line 275, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  17239362 ps: (keymgr_csr_assert_fpv.sv:376) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  17239362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_bit_bash has 4 failures.

0.keymgr_csr_bit_bash.2261611408
Line 256, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 1402993999 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 1402993999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_bit_bash.2573424492
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 1884852644 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 1884852644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 6 failures.

1.keymgr_shadow_reg_errors_with_csr_rw.465662756
Line 259, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  80290174 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  80290174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_shadow_reg_errors_with_csr_rw.3855167417
Line 258, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  58632258 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  58632258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_aliasing has 1 failures.

1.keymgr_csr_aliasing.4015044415
Line 256, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 241267618 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 241267618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_rw has 4 failures.

3.keymgr_csr_rw.3323002454
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  12444501 ps: (keymgr_csr_assert_fpv.sv:381) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  12444501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_rw.2193001298
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @  39662718 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @  39662718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

... and 1 more tests.

UVM_ERROR (keymgr_scoreboard.sv:1019) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 6 failures:

Test keymgr_kmac_rsp_err has 6 failures.

0.keymgr_kmac_rsp_err.511381509
Line 357, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  34725588 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (457945497229065070827611163731444324722576320613307329935596302286110814969497557283838256140183220889694676972977895758035702204806768334065645241647343387150672475865388852139417953746066116872298469937818772459158917100413878459791503458739025900380530039559364609250156484779083083078447945570574105210628500841988302348342933504852800886773704848330913948673885599439201722883614276961423118147192516387066780152717158928452412411706294180281836593478219128 [0x30a3768a00000000c69021bcdbcd19613a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9244deaf4f2f984c1ca10bce02141528dc278035dd65a8857ebbc0319d40ae1e5f785d207fa147337b3f9af95ab1d011cc89bf6062b71a7aa14133e6417c96dcd8824c10aa5177df020e25eba8c0fd488f454acd341bee63cdb2b6171356ca4866878e3aba161291d4af362ab0129941d77aea5cba2d630ea828c96b5d91783678cb4f1fa1c8af678e0448d384f09b578] vs 457945497229065070827611163731444324722576320613307329935596302286110814969497557283838256140183220889694676972977895758035702204806768334065645241647343387150672475865388852139417953746066116872298469937818772459158917100413878459791503458739025900380530039559364609250156484779083083078447945570574105210628500841988302348342933504852800886773704848330913948673885599439201722883614276961423118147192516387066780152717158928452412411706294180281836593478219128 [0x30a3768a00000000c69021bcdbcd19613a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9244deaf4f2f984c1ca10bce02141528dc278035dd65a8857ebbc0319d40ae1e5f785d207fa147337b3f9af95ab1d011cc89bf6062b71a7aa14133e6417c96dcd8824c10aa5177df020e25eba8c0fd488f454acd341bee63cdb2b6171356ca4866878e3aba161291d4af362ab0129941d77aea5cba2d630ea828c96b5d91783678cb4f1fa1c8af678e0448d384f09b578]) cdi_type: Attestation
  
   DiversificationKey act: 0x77aea5cba2d630ea828c96b5d91783678cb4f1fa1c8af678e0448d384f09b578, exp: 0x77aea5cba2d630ea828c96b5d91783678cb4f1fa1c8af678e0448d384f09b578
   RomDigests act: 0xc89bf6062b71a7aa14133e6417c96dcd8824c10aa5177df020e25eba8c0fd488f454acd341bee63cdb2b6171356ca4866878e3aba161291d4af362ab0129941d, exp: 0xc89bf6062b71a7aa14133e6417c96dcd8824c10aa5177df020e25eba8c0fd488f454acd341bee63cdb2b6171356ca4866878e3aba161291d4af362ab0129941d
   HealthMeasurement act: 0xf785d207fa147337b3f9af95ab1d011c, exp: 0xf785d207fa147337b3f9af95ab1d011c

3.keymgr_kmac_rsp_err.3654789855
Line 334, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 742443132 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (33794334264621909766708096523458882990077955804478525202742483836392308153377208666759886886359654058599202149406416638568200279371965904681102729487379764744059305574657760419975107658858487014970411491571217636914985108463092629910553557494532014828067700165158179253727789852826333049963886811009406039556451958732630136605920658321291519386629914298352352734332809504867181070305132197260153528715792308684301199450404892140041136298881362094036622129971616754891200460301659000 [0xc293a1942f04cf0680132205b950652e00000000c22a585f3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507a20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 33794334264621909766708096523458882990077955804478525202742483836392308153377208666759886886359654058599202149406416638568200279371965904681102729487379764744059305574657760419975107658858487014970411491571217636914985108463092629910553557494532014828067700165158179253727789852826333049963886811009406039556451958732630136605920658321291519386629914298352352734332809504867181070305132197260153528715792308684301199450404892140041136298881362094036622129971616754891200460301659000 [0xc293a1942f04cf0680132205b950652e00000000c22a585f3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507a20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigests act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507a20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507a20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

... and 4 more failures.

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 2 failures.

6.keymgr_stress_all.1717704565
Line 299, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all/latest/run.log

  UVM_ERROR @   9699087 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   9699087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.keymgr_stress_all.2224170147
Line 4046, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2205998490 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 2205998490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_hwsw_invalid_input has 1 failures.

44.keymgr_hwsw_invalid_input.2756187564
Line 406, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @   7935797 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   7935797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 11.keymgr_stress_all_with_rand_reset.3983673906
    Line 437, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  71601447 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @  71601447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.keymgr_stress_all_with_rand_reset.1900472844
    Line 1060, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 333169151 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 333169151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1017) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

4.keymgr_stress_all_with_rand_reset.785085441
Line 857, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 920509106 ps: (keymgr_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed act == exp (312943785278975791843596117222458601861520741346430767448542319600494205817027430856318951616987999139201195220288629789630847115992056044939292489388371325191667369494903037838688241167298265627258063105401769993128068585355160667169216986369171633892224671476115053877932900644214482182209287319645558846552954867528280206299880613683933930465382734271233379620914634075873761577237477340880303907708060642202963329731906998144161779343738541871458991894119504426963605250260644359231651686542250702 [0x61ad618cd9bb55fccf143a64efe41c263246b391fc935468b060aa8c6d0578673a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9a03f365d005cdf75391d1f20b1d0c21284095962174db00a865e1bcb928f0dec1f4aee25867171be79f554863e15868d7305108c7e5aa01fe4ada4421ec8d1bc2352040ff787a8fc8f94987f329e7e3708300c0469bbc2c7cf597543fd15760bc012266677c9aab5f406c5f99d280a1d955a2c8dbab43849b60c62bb9354607d361cade985de459bba01285863b492ce] vs 153041108517711907890398263283622123182323985403144660646509292776423793966172312596219143074986175828041641987962249185169977310452387538264264628504774544481345890190271154057920860704325430575744056983150518498028393727523412655439277058573508040088218882177748369535592007478394223584793188090957898257161130255515128104739089750887275116281667776807749570047831658347527799298085471641258235033621774733825222915995590121208825847557050953484774062524091831112672649615100765070120961869220188878 [0x2fc48eda78fbd6adb37ee3076cd0a37cb76ef48f2441755d1a02953506f5b65f3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9a03f365d005cdf75391d1f20b1d0c21284095962174db00a865e1bcb928f0dec1f4aee25867171be79f554863e15868d7305108c7e5aa01fe4ada4421ec8d1bc2352040ff787a8fc8f94987f329e7e3708300c0469bbc2c7cf597543fd15760bc012266677c9aab5f406c5f99d280a1d955a2c8dbab43849b60c62bb9354607d361cade985de459bba01285863b492ce]) cdi_type: Attestation
  
   DiversificationKey act: 0x955a2c8dbab43849b60c62bb9354607d361cade985de459bba01285863b492ce, exp: 0x955a2c8dbab43849b60c62bb9354607d361cade985de459bba01285863b492ce
   RomDigests act: 0x7305108c7e5aa01fe4ada4421ec8d1bc2352040ff787a8fc8f94987f329e7e3708300c0469bbc2c7cf597543fd15760bc012266677c9aab5f406c5f99d280a1d, exp: 0x7305108c7e5aa01fe4ada4421ec8d1bc2352040ff787a8fc8f94987f329e7e3708300c0469bbc2c7cf597543fd15760bc012266677c9aab5f406c5f99d280a1d
   HealthMeasurement act: 0x1f4aee25867171be79f554863e15868d, exp: 0x1f4aee25867171be79f554863e15868d

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 30.keymgr_stress_all_with_rand_reset.2958504453
    Line 1614, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 638276322 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (157175561 [0x95e4f09] vs 157175561 [0x95e4f09])
  UVM_INFO @ 638276322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```