KEYMGR Simulation Results

Saturday May 18 2024 19:02:26 UTC

GitHub Revision: `628dfc9516`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 224585352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.270s	1.576ms	50	50	100.00
V1	random	keymgr_random	1.601m	10.475ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.530s	129.252us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.740s	59.009us	17	20	85.00
V1	csr_bit_bash	keymgr_csr_bit_bash	26.170s	870.468us	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	10.050s	2.744ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.560s	23.555us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.740s	59.009us	17	20	85.00
		keymgr_csr_aliasing	10.050s	2.744ms	5	5	100.00
V1		TOTAL			150	155	96.77
V2	cfgen_during_op	keymgr_cfg_regwen	2.054m	2.832ms	48	50	96.00
V2	sideload	keymgr_sideload	57.050s	16.833ms	50	50	100.00
		keymgr_sideload_kmac	53.800s	3.756ms	50	50	100.00
		keymgr_sideload_aes	49.440s	7.111ms	50	50	100.00
		keymgr_sideload_otbn	1.056m	10.617ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	26.510s	4.561ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	9.000s	1.113ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.563m	5.148ms	45	50	90.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.370m	2.541ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.215m	2.848ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	32.870s	4.513ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.182m	86.297ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.920s	12.039us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.170s	28.602us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	7.200s	2.497ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	7.200s	2.497ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.530s	129.252us	5	5	100.00
		keymgr_csr_rw	1.740s	59.009us	17	20	85.00
		keymgr_csr_aliasing	10.050s	2.744ms	5	5	100.00
		keymgr_same_csr_outstanding	3.650s	89.665us	10	20	50.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.530s	129.252us	5	5	100.00
		keymgr_csr_rw	1.740s	59.009us	17	20	85.00
		keymgr_csr_aliasing	10.050s	2.744ms	5	5	100.00
		keymgr_same_csr_outstanding	3.650s	89.665us	10	20	50.00
V2		TOTAL			721	740	97.43
V2S	sec_cm_additional_check	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
		keymgr_tl_intg_err	40.990s	1.352ms	10	20	50.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	41.760s	3.396ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	41.760s	3.396ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	41.760s	3.396ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	41.760s	3.396ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.390s	408.778us	13	20	65.00
V2S	prim_count_check	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	40.990s	1.352ms	10	20	50.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	41.760s	3.396ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.054m	2.832ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.601m	10.475ms	50	50	100.00
		keymgr_csr_rw	1.740s	59.009us	17	20	85.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.601m	10.475ms	50	50	100.00
		keymgr_csr_rw	1.740s	59.009us	17	20	85.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.601m	10.475ms	50	50	100.00
		keymgr_csr_rw	1.740s	59.009us	17	20	85.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	9.000s	1.113ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.215m	2.848ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.215m	2.848ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.601m	10.475ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	29.280s	1.562ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	43.230s	4.686ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	9.000s	1.113ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	43.230s	4.686ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	43.230s	4.686ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	43.230s	4.686ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.183m	39.202ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	43.230s	4.686ms	50	50	100.00
V2S		TOTAL			148	165	89.70
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	16.550s	1.068ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1062	1110	95.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	16	16	12	75.00
V2S	6	6	4	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.87	99.10	97.91	98.88	100.00	99.12	98.41	91.68

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 32 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 7 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.1695126955
Line 266, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @ 136256545 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @ 136256545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_shadow_reg_errors_with_csr_rw.1004531224
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  45104458 ps: (keymgr_csr_assert_fpv.sv:381) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  45104458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_tl_intg_err has 10 failures.

0.keymgr_tl_intg_err.2087654757
Line 272, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  40573445 ps: (keymgr_csr_assert_fpv.sv:376) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  40573445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_tl_intg_err.390293769
Line 262, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  36811315 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  36811315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test keymgr_same_csr_outstanding has 10 failures.

0.keymgr_same_csr_outstanding.761515104
Line 259, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  61123737 ps: (keymgr_csr_assert_fpv.sv:376) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  61123737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_same_csr_outstanding.1385736228
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @ 108415107 ps: (keymgr_csr_assert_fpv.sv:386) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @ 108415107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test keymgr_csr_bit_bash has 2 failures.

1.keymgr_csr_bit_bash.2995144062
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @ 4731695671 ps: (keymgr_csr_assert_fpv.sv:381) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @ 4731695671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_bit_bash.1581005424
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 1564827206 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 1564827206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_rw has 3 failures.

9.keymgr_csr_rw.1733429583
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @   8154881 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @   8154881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.keymgr_csr_rw.1170845385
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  17101109 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  17101109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1019) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 5 failures:

Test keymgr_kmac_rsp_err has 5 failures.

6.keymgr_kmac_rsp_err.3749374815
Line 445, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  22118058 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (154286523993226651265651730860806310876472829220525936304733906424732122521039507763888664499106593852059625186182106994078335740205600403196857868420621581179192326042630721913465508594337160834038370781048395271946766300561175549856311575265594789827604757042054428948017360709377629448420673800192719115850898993867137316285290380955205918679468891481579934506253487877449462108914870522126591705277119412524032387026463031233369245314351471534377835569676878673992024504007258556608214124009798384 [0x302812463cc5fee00000000034adec2d000000006d3e1e05245c1056cb1fd5da3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f956c05d9739c5c8884e63d932eb299f365f825eca5b4672e0463d454c173283adf542813d47505e54636cc6569cbacf8fbeb93fa470622358f34edf9201f3ffcac595a43260f778895289f04fb535a35be4966ae0b3395557634e32cc61a87ee26990fc94d2d119eb470f7f0bd9a6a44183a5a839e6482551c52ca60461695446dc182e7569a06478bcf46a4e0a6abaf0] vs 154286523993226651265651730860806310876472829220525936304733906424732122521039507763888664499106593852059625186182106994078335740205600403196857868420621581179192326042630721913465508594337160834038370781048395271946766300561175549856311575265594789827604757042054428948017360709377629448420673800192719115850898993867137316285290380955205918679468891481579934506253487877449462108914870522126591705277119412524032387026463031233369245314351471534377835569676878673992024504007258556608214124009798384 [0x302812463cc5fee00000000034adec2d000000006d3e1e05245c1056cb1fd5da3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f956c05d9739c5c8884e63d932eb299f365f825eca5b4672e0463d454c173283adf542813d47505e54636cc6569cbacf8fbeb93fa470622358f34edf9201f3ffcac595a43260f778895289f04fb535a35be4966ae0b3395557634e32cc61a87ee26990fc94d2d119eb470f7f0bd9a6a44183a5a839e6482551c52ca60461695446dc182e7569a06478bcf46a4e0a6abaf0]) cdi_type: Attestation
  
   DiversificationKey act: 0x83a5a839e6482551c52ca60461695446dc182e7569a06478bcf46a4e0a6abaf0, exp: 0x83a5a839e6482551c52ca60461695446dc182e7569a06478bcf46a4e0a6abaf0
   RomDigests act: 0xbeb93fa470622358f34edf9201f3ffcac595a43260f778895289f04fb535a35be4966ae0b3395557634e32cc61a87ee26990fc94d2d119eb470f7f0bd9a6a441, exp: 0xbeb93fa470622358f34edf9201f3ffcac595a43260f778895289f04fb535a35be4966ae0b3395557634e32cc61a87ee26990fc94d2d119eb470f7f0bd9a6a441
   HealthMeasurement act: 0xf542813d47505e54636cc6569cbacf8f, exp: 0xf542813d47505e54636cc6569cbacf8f

7.keymgr_kmac_rsp_err.2578782318
Line 326, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 216124567 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (1605930754565491250042339328357387143542526556207941497641627338815315533913333777087469357870163031245441064493462708077771377181009926179659700513805395776358991867360255325993717174722529139505180508996569177846385315344564642717351071380078912761821312123316138919770079272518653124591138091308118034045960615061520653279100622783276138403123835316190489736808562610037056126677203362899860124604737239572204439644026418 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f95693493f9bd5a509b0601adc20a775724cfc7f097d3b48c05427532184951c50641e46375d22700baeacfef09d419d29df1e71085a6f0bc4924f4d2cdf09121bc5644d61f71e33736eca7ca06d445de23d6ee8b2daa8812fecd5ab0c01d87bcdebb92080ae56d0642fdfa9a71e72a8153de2190d40831654dd8016a4b312b0596d0ffdc11913ed1544e1829c68de3632] vs 1605930754565491250042339328357387143542526556207941497641627338815315533913333777087469357870163031245441064493462708077771377181009926179659700513805395776358991867360255325993717174722529139505180508996569177846385315344564642717351071380078912761821312123316138919770079272518653124591138091308118034045960615061520653279100622783276138403123835316190489736808562610037056126677203362899860124604737239572204439644026418 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f95693493f9bd5a509b0601adc20a775724cfc7f097d3b48c05427532184951c50641e46375d22700baeacfef09d419d29df1e71085a6f0bc4924f4d2cdf09121bc5644d61f71e33736eca7ca06d445de23d6ee8b2daa8812fecd5ab0c01d87bcdebb92080ae56d0642fdfa9a71e72a8153de2190d40831654dd8016a4b312b0596d0ffdc11913ed1544e1829c68de3632]) cdi_type: Attestation
  
   DiversificationKey act: 0x3de2190d40831654dd8016a4b312b0596d0ffdc11913ed1544e1829c68de3632, exp: 0x3de2190d40831654dd8016a4b312b0596d0ffdc11913ed1544e1829c68de3632
   RomDigests act: 0xdf1e71085a6f0bc4924f4d2cdf09121bc5644d61f71e33736eca7ca06d445de23d6ee8b2daa8812fecd5ab0c01d87bcdebb92080ae56d0642fdfa9a71e72a815, exp: 0xdf1e71085a6f0bc4924f4d2cdf09121bc5644d61f71e33736eca7ca06d445de23d6ee8b2daa8812fecd5ab0c01d87bcdebb92080ae56d0642fdfa9a71e72a815
   HealthMeasurement act: 0x641e46375d22700baeacfef09d419d29, exp: 0x641e46375d22700baeacfef09d419d29

... and 3 more failures.

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 4 failures:

Test keymgr_stress_all_with_rand_reset has 4 failures.

28.keymgr_stress_all_with_rand_reset.1063298415
Line 889, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  74448132 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @  74448132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.keymgr_stress_all_with_rand_reset.1264631774
Line 782, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 141581380 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 141581380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 1 failures.

3.keymgr_stress_all.2157695753
Line 811, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 490435385 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 490435385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 2 failures.

33.keymgr_cfg_regwen.1835595060
Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  19344468 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  19344468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.keymgr_cfg_regwen.2048086879
Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @   2876649 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2876649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 2 failures:

Test keymgr_stress_all_with_rand_reset has 2 failures.

9.keymgr_stress_all_with_rand_reset.2449342777
Line 1145, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 114944295 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (259545009 [0xf7857b1] vs 259545009 [0xf7857b1])
  UVM_INFO @ 114944295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.keymgr_stress_all_with_rand_reset.4148118582
Line 469, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 239246338 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3269953403 [0xc2e7877b] vs 3269953403 [0xc2e7877b])
  UVM_INFO @ 239246338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1017) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

17.keymgr_stress_all_with_rand_reset.609163987
Line 1020, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 492080370 ps: (keymgr_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed act == exp (445619793303383927609311197637677594141886377540326971368930014665457974778673908256674637303875517549788853510395536783902754084987961740391390174639890500077126352125269568864086928413002761337950380932781786621797203725803097451371543170352304266535797395791246852183869237601128172478786681647700274637336714783851879010507601053412042545463291770805564286202752267213149270345018411147137535357580323229447196280477807753364554037028620132448936138848770050244624829231582547011951444118401331057 [0x8b16b0f500000000000000008161776461df6d778cc1ab840e32d786c94fab913a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f995aa195c58c7a7bd1bb1ce37bb8d7f103b5ac7a6599fb7b84cf6dadd7c97c8854a8b98894a6e4dfd2cef98612e3cf43e0887d3b78689edb161f3a47f26d41b2934c2a17c519cd90460be8c42350ea7f2cdcbbede95d7af1d273719b025bb06bca227b25b6b902369ea3127631ec2da84dcc003b27fa81e2a120a407e1119b5d2b851951c81415f2048429847fc1e2f71] vs 1605930754565491250042339328357387143542526556207941497641627338815315533913348852508891936759552204903299522193359105683019877293558138282852526517930332861132582511336110342322931976901355683911205435675300134143471063209441603204006986583105483162044660017943264138904680869752807895578966507503504954650374509476840162909855320136799336972778635194364017689074877337412853272297965179160383331642427664026878867442380657 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f995aa195c58c7a7bd1bb1ce37bb8d7f103b5ac7a6599fb7b84cf6dadd7c97c8854a8b98894a6e4dfd2cef98612e3cf43e0887d3b78689edb161f3a47f26d41b2934c2a17c519cd90460be8c42350ea7f2cdcbbede95d7af1d273719b025bb06bca227b25b6b902369ea3127631ec2da84dcc003b27fa81e2a120a407e1119b5d2b851951c81415f2048429847fc1e2f71]) cdi_type: Attestation
  
   DiversificationKey act: 0xdcc003b27fa81e2a120a407e1119b5d2b851951c81415f2048429847fc1e2f71, exp: 0xdcc003b27fa81e2a120a407e1119b5d2b851951c81415f2048429847fc1e2f71
   RomDigests act: 0x887d3b78689edb161f3a47f26d41b2934c2a17c519cd90460be8c42350ea7f2cdcbbede95d7af1d273719b025bb06bca227b25b6b902369ea3127631ec2da84, exp: 0x887d3b78689edb161f3a47f26d41b2934c2a17c519cd90460be8c42350ea7f2cdcbbede95d7af1d273719b025bb06bca227b25b6b902369ea3127631ec2da84
   HealthMeasurement act: 0x4a8b98894a6e4dfd2cef98612e3cf43e, exp: 0x4a8b98894a6e4dfd2cef98612e3cf43e

UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 45.keymgr_stress_all.2357886460
    Line 4440, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1396546368 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2658997546 [0x9e7d152a] vs 4183981906 [0xf9627f52]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 1396546368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```