KEYMGR Simulation Results

Saturday May 25 2024 19:02:40 UTC

GitHub Revision: `3216fab097`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1830339797

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	46.760s	2.082ms	50	50	100.00
V1	random	keymgr_random	34.190s	6.366ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.430s	33.004us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.500s	53.939us	15	20	75.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.440s	1.040ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	10.320s	375.972us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.060s	40.163us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.500s	53.939us	15	20	75.00
		keymgr_csr_aliasing	10.320s	375.972us	4	5	80.00
V1		TOTAL			148	155	95.48
V2	cfgen_during_op	keymgr_cfg_regwen	2.090m	23.643ms	50	50	100.00
V2	sideload	keymgr_sideload	42.790s	11.482ms	50	50	100.00
		keymgr_sideload_kmac	49.380s	1.673ms	50	50	100.00
		keymgr_sideload_aes	1.091m	9.479ms	50	50	100.00
		keymgr_sideload_otbn	52.470s	11.745ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	43.240s	1.548ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	10.750s	227.138us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.875m	5.844ms	39	50	78.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.620m	15.495ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.281m	10.877ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	9.410s	1.039ms	49	50	98.00
V2	stress_all	keymgr_stress_all	3.612m	8.876ms	50	50	100.00
V2	intr_test	keymgr_intr_test	0.930s	21.439us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.970s	15.350us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.580s	812.956us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.580s	812.956us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.430s	33.004us	5	5	100.00
		keymgr_csr_rw	1.500s	53.939us	15	20	75.00
		keymgr_csr_aliasing	10.320s	375.972us	4	5	80.00
		keymgr_same_csr_outstanding	4.080s	1.486ms	12	20	60.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.430s	33.004us	5	5	100.00
		keymgr_csr_rw	1.500s	53.939us	15	20	75.00
		keymgr_csr_aliasing	10.320s	375.972us	4	5	80.00
		keymgr_same_csr_outstanding	4.080s	1.486ms	12	20	60.00
V2		TOTAL			718	740	97.03
V2S	sec_cm_additional_check	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
		keymgr_tl_intg_err	1.410m	13.276ms	14	20	70.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	30.270s	1.100ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	30.270s	1.100ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	30.270s	1.100ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	30.270s	1.100ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.580s	647.166us	16	20	80.00
V2S	prim_count_check	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.410m	13.276ms	14	20	70.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	30.270s	1.100ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.090m	23.643ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	34.190s	6.366ms	50	50	100.00
		keymgr_csr_rw	1.500s	53.939us	15	20	75.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	34.190s	6.366ms	50	50	100.00
		keymgr_csr_rw	1.500s	53.939us	15	20	75.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	34.190s	6.366ms	50	50	100.00
		keymgr_csr_rw	1.500s	53.939us	15	20	75.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	10.750s	227.138us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.281m	10.877ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.281m	10.877ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	34.190s	6.366ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.440s	3.292ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	27.230s	1.378ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	10.750s	227.138us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	27.230s	1.378ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	27.230s	1.378ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	27.230s	1.378ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	3.088m	8.285ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	27.230s	1.378ms	50	50	100.00
V2S		TOTAL			155	165	93.94
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	15.800s	1.015ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1065	1110	95.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	4	57.14
V2	16	16	11	68.75
V2S	6	6	4	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.88	99.10	97.99	98.76	100.00	99.12	98.41	91.81

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 25 failures:

Test keymgr_same_csr_outstanding has 8 failures.

0.keymgr_same_csr_outstanding.2324174314
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  46584966 ps: (keymgr_csr_assert_fpv.sv:371) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  46584966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_same_csr_outstanding.1837241724
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  74346018 ps: (keymgr_csr_assert_fpv.sv:376) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  74346018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_tl_intg_err has 6 failures.

1.keymgr_tl_intg_err.632312955
Line 265, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @   7454638 ps: (keymgr_csr_assert_fpv.sv:381) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @   7454638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_tl_intg_err.2181593593
Line 279, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  49354367 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  49354367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_rw has 5 failures.

1.keymgr_csr_rw.3568833703
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  45292144 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  45292144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_rw.2132213304
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  21029111 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  21029111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_bit_bash has 1 failures.

4.keymgr_csr_bit_bash.41773674
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 452375086 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 452375086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_aliasing has 1 failures.

4.keymgr_csr_aliasing.3535316692
Line 256, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 859617092 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 859617092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_ERROR (keymgr_scoreboard.sv:1019) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 10 failures:

Test keymgr_kmac_rsp_err has 10 failures.

1.keymgr_kmac_rsp_err.809108213
Line 442, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 151143220 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (1605930754565491250042339328357387143542526556207941497641627338815315533913340119058275539538972641043009804922243622708244696045369904233294448004756970398174643750111413695079180600583552263641534540754728133035964106272562642561382937943991898225584608817159856336937169978223962558673331826461458529892433503204347937690769336838761952810006660110821978057232452099626642292434490058034144877487296831954786710225255213 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9711da7d9f02c208ce372a7012dd331c8329c72ba2805c0fc5256a60b3b7401e8c81e32a36a22c3f2c5b95d9cd6af68cc8d9d277aa8ccd7aad9d68dba186878237d547870a5e3f1d8c55c70c498cd778f73e7d47d40a14090ebc94d9f66ab6062c8fa0032a1568371a61f2eedb5a1db222a61a6a48047fcfe2e39f599f2077522aed7658b4bb67f727513c9d620d97b2d] vs 1605930754565491250042339328357387143542526556207941497641627338815315533913340119058275539538972641043009804922243622708244696045369904233294448004756970398174643750111413695079180600583552263641534540754728133035964106272562642561382937943991898225584608817159856336937169978223962558673331826461458529892433503204347937690769336838761952810006660110821978057232452099626642292434490058034144877487296831954786710225255213 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9711da7d9f02c208ce372a7012dd331c8329c72ba2805c0fc5256a60b3b7401e8c81e32a36a22c3f2c5b95d9cd6af68cc8d9d277aa8ccd7aad9d68dba186878237d547870a5e3f1d8c55c70c498cd778f73e7d47d40a14090ebc94d9f66ab6062c8fa0032a1568371a61f2eedb5a1db222a61a6a48047fcfe2e39f599f2077522aed7658b4bb67f727513c9d620d97b2d]) cdi_type: Attestation
  
   DiversificationKey act: 0x2a61a6a48047fcfe2e39f599f2077522aed7658b4bb67f727513c9d620d97b2d, exp: 0x2a61a6a48047fcfe2e39f599f2077522aed7658b4bb67f727513c9d620d97b2d
   RomDigests act: 0x8d9d277aa8ccd7aad9d68dba186878237d547870a5e3f1d8c55c70c498cd778f73e7d47d40a14090ebc94d9f66ab6062c8fa0032a1568371a61f2eedb5a1db22, exp: 0x8d9d277aa8ccd7aad9d68dba186878237d547870a5e3f1d8c55c70c498cd778f73e7d47d40a14090ebc94d9f66ab6062c8fa0032a1568371a61f2eedb5a1db22
   HealthMeasurement act: 0xc81e32a36a22c3f2c5b95d9cd6af68cc, exp: 0xc81e32a36a22c3f2c5b95d9cd6af68cc

3.keymgr_kmac_rsp_err.1053862974
Line 532, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 143352574 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (621709066213437687722565452722392846102503147149514277721803416570444555615868134885585468636797125197714782249058115814570797658949421535249878975862826224823783758874138093752395157861370577680646913035812251841745556935571423771379971933428400644290792255848936087825224773516423779944370243161331778753813090480672650987797877420297097309893148234269269264080832665854054604919750539551444178057112805017011387532258067584192845030031366887411737441768014687739566488226174356923654751355737131906 [0xc20ce24afde2f2a8bdf8a14363aaba74725f0f79ed350f6eda6790f0aa89e0253a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9036f6bd7080e008ee975c24b159c2a54bf8c6bce57acf4dd4aeb8a777411005cc846d7ab36472f40e334acfc36cf3be2fc174da719eee141d5b98b2dd79e6398129b379f8e8f449b69c38c2af11db0e74e1fae77ed139d79c00ff1e502ddce5b8969fc31d10bbb15b29692eabfe6a4b57ec40b99201a710d4e23e9bc1d6585266fe7622afdd856fd726e9867f0f6cb82] vs 621709066213437687722565452722392846102503147149514277721803416570444555615868134885585468636797125197714782249058115814570797658949421535249878975862826224823783758874138093752395157861370577680646913035812251841745556935571423771379971933428400644290792255848936087825224773516423779944370243161331778753813090480672650987797877420297097309893148234269269264080832665854054604919750539551444178057112805017011387532258067584192845030031366887411737441768014687739566488226174356923654751355737131906 [0xc20ce24afde2f2a8bdf8a14363aaba74725f0f79ed350f6eda6790f0aa89e0253a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9036f6bd7080e008ee975c24b159c2a54bf8c6bce57acf4dd4aeb8a777411005cc846d7ab36472f40e334acfc36cf3be2fc174da719eee141d5b98b2dd79e6398129b379f8e8f449b69c38c2af11db0e74e1fae77ed139d79c00ff1e502ddce5b8969fc31d10bbb15b29692eabfe6a4b57ec40b99201a710d4e23e9bc1d6585266fe7622afdd856fd726e9867f0f6cb82]) cdi_type: Attestation
  
   DiversificationKey act: 0x7ec40b99201a710d4e23e9bc1d6585266fe7622afdd856fd726e9867f0f6cb82, exp: 0x7ec40b99201a710d4e23e9bc1d6585266fe7622afdd856fd726e9867f0f6cb82
   RomDigests act: 0xfc174da719eee141d5b98b2dd79e6398129b379f8e8f449b69c38c2af11db0e74e1fae77ed139d79c00ff1e502ddce5b8969fc31d10bbb15b29692eabfe6a4b5, exp: 0xfc174da719eee141d5b98b2dd79e6398129b379f8e8f449b69c38c2af11db0e74e1fae77ed139d79c00ff1e502ddce5b8969fc31d10bbb15b29692eabfe6a4b5
   HealthMeasurement act: 0xc846d7ab36472f40e334acfc36cf3be2, exp: 0xc846d7ab36472f40e334acfc36cf3be2

... and 8 more failures.

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 4 failures:

Test keymgr_stress_all_with_rand_reset has 4 failures.

10.keymgr_stress_all_with_rand_reset.1777638020
Line 667, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 466271116 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 466271116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.keymgr_stress_all_with_rand_reset.4143111535
Line 803, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  85990038 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @  85990038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

Test keymgr_kmac_rsp_err has 1 failures.

6.keymgr_kmac_rsp_err.2517806493
Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  11721379 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  11721379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_otbn has 1 failures.

33.keymgr_sideload_otbn.3969643603
Line 280, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest/run.log

  UVM_ERROR @  11666335 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  11666335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 6.keymgr_sync_async_fault_cross.3976187918
    Line 333, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  84476616 ps: (cip_base_scoreboard.sv:241) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  84476616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 16.keymgr_stress_all_with_rand_reset.2820690818
    Line 652, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  53396093 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1778905058 [0x6a07efe2] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @  53396093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1017) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

24.keymgr_stress_all_with_rand_reset.1842556445
Line 1324, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 626632734 ps: (keymgr_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed act == exp (156072655101259384496066018879226304597919342929381144554064805350705765577429240229870154780102599525312749645011374285383776307633395672691307747009133952069446151274119130812492861702581841697011729005826101608561246770252410983702127092482182028334396510160013489437516662940737997184044454760016600438099122543650828750375754449932580829452428387999653788341846696942493170944549099785080952688360988685326532714426329026731930875061736031508572053498096659210760437896413731288716209609 [0xd139a28f6f2726e9d17e6896000000003641bd4f76fba6b9000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f99dad6e8e72cfd08f3d7290ba819e8c1c2fa2905a6a21255d3307d3d99137d7fe8784bd3d6b2473970299f9e21292a24f3eaac7552da205069d7e7d670ee8805617c0931ec618a9e344d4a910a711614f907f447f069eff1a112adf5cf82ed6da1a8a4810e53d96798132965cc9da86299c0f107851eb95bf0240990d8378ed3fb0df56021db07b363fc364c82d84edc9] vs 5679158498423866595573893991443656965538326139632893257373560009315623080850905519116224302161965243179521432745721337237001950160699818211622570516577375003476338470142726500921419106275152362449773958011290690429099259725861235845135629144877961122315706237666004414401658027528653933019637951234701252152599707932729400654773962050335289397505138687126819128670249734901233345087900338880691823672260601032790821790748115915133950199332274008919600882770200177083215305 [0x8c70a26ae549a9da0000000000000000000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f99dad6e8e72cfd08f3d7290ba819e8c1c2fa2905a6a21255d3307d3d99137d7fe8784bd3d6b2473970299f9e21292a24f3eaac7552da205069d7e7d670ee8805617c0931ec618a9e344d4a910a711614f907f447f069eff1a112adf5cf82ed6da1a8a4810e53d96798132965cc9da86299c0f107851eb95bf0240990d8378ed3fb0df56021db07b363fc364c82d84edc9]) cdi_type: Attestation
  
   DiversificationKey act: 0x9c0f107851eb95bf0240990d8378ed3fb0df56021db07b363fc364c82d84edc9, exp: 0x9c0f107851eb95bf0240990d8378ed3fb0df56021db07b363fc364c82d84edc9
   RomDigests act: 0x3eaac7552da205069d7e7d670ee8805617c0931ec618a9e344d4a910a711614f907f447f069eff1a112adf5cf82ed6da1a8a4810e53d96798132965cc9da8629, exp: 0x3eaac7552da205069d7e7d670ee8805617c0931ec618a9e344d4a910a711614f907f447f069eff1a112adf5cf82ed6da1a8a4810e53d96798132965cc9da8629
   HealthMeasurement act: 0x8784bd3d6b2473970299f9e21292a24f, exp: 0x8784bd3d6b2473970299f9e21292a24f

UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 38.keymgr_lc_disable.1573316771
    Line 341, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  99706269 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (3313363163 [0xc57de8db] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
  UVM_INFO @  99706269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```