KEYMGR_DPE Simulation Results

Saturday May 04 2024 19:02:32 UTC

GitHub Revision: `f4962c85dd`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1307141976

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	5.614m	45.484ms	47	50	94.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.060s	65.659us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.290s	43.994us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	22.130s	3.701ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	7.510s	308.490us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.730s	23.978us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.290s	43.994us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.510s	308.490us	5	5	100.00
V1		TOTAL			102	105	97.14
V2	intr_test	keymgr_dpe_intr_test	0.940s	13.877us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.050s	25.292us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.200s	144.995us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.200s	144.995us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.060s	65.659us	5	5	100.00
		keymgr_dpe_csr_rw	1.290s	43.994us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.510s	308.490us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.590s	146.627us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.060s	65.659us	5	5	100.00
		keymgr_dpe_csr_rw	1.290s	43.994us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.510s	308.490us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.590s	146.627us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	11.920s	5.789ms	5	5	100.00
		keymgr_dpe_tl_intg_err	8.980s	332.220us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.450s	1.268ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.450s	1.268ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.450s	1.268ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.450s	1.268ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	8.090s	471.514us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	11.920s	5.789ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	11.920s	5.789ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			307	310	99.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.26	97.70	90.58	57.52	76.92	94.94	98.34	17.78

Failure Buckets

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 2 failures:

Test keymgr_dpe_smoke has 2 failures.

28.keymgr_dpe_smoke.1831907889
Line 2410, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/28.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 117075522 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hc4426b357b029b7a9ecf9324bee5412e5f86189a1a78b32ce1e41ed547ecab3d3ff0d2bec1605870a1fe3ccd74468864669fc6920a9c0e1b4ca1fe446db74042 vs. act 'h0
  UVM_INFO @ 117075522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.keymgr_dpe_smoke.2157794718
Line 2555, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/33.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 628859409 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h77b4e9e361f6ea1f46c7a47c608f78d6123d8d267254dc4d074589dab8d2508397c287a3aedda534095af0e686112b1e3c9788a5deefa571792e34ea99432bbd vs. act 'h0
  UVM_INFO @ 628859409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_dpe_smoke has 1 failures.
  - 44.keymgr_dpe_smoke.368610691
    Line 2686, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/44.keymgr_dpe_smoke/latest/run.log
```
  UVM_ERROR @ 453390672 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 453390672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```