KEYMGR_DPE Simulation Results

Saturday May 18 2024 19:02:26 UTC

GitHub Revision: `628dfc9516`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 224585352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	2.458m	11.867ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.280s	212.107us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.350s	45.840us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	11.670s	1.784ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	6.130s	708.315us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.760s	20.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.350s	45.840us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.130s	708.315us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	1.000s	22.244us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.110s	147.862us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.320s	590.391us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.320s	590.391us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.280s	212.107us	5	5	100.00
		keymgr_dpe_csr_rw	1.350s	45.840us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.130s	708.315us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.980s	356.029us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.280s	212.107us	5	5	100.00
		keymgr_dpe_csr_rw	1.350s	45.840us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.130s	708.315us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.980s	356.029us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	14.150s	550.784us	5	5	100.00
		keymgr_dpe_tl_intg_err	8.880s	241.822us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.520s	588.251us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.520s	588.251us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.520s	588.251us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.520s	588.251us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.320s	3.281ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	14.150s	550.784us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	14.150s	550.784us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			309	310	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.26	97.60	90.64	57.52	76.92	94.97	98.34	17.82

Failure Buckets

UVM_ERROR (keymgr_dpe_scoreboard.sv:564) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act *

has 1 failures:

Test keymgr_dpe_smoke has 1 failures.

4.keymgr_dpe_smoke.1691606632
Line 3411, in log /container/opentitan-public/scratch/os_regression/keymgr_dpe-sim-vcs/4.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 3077440689 ps: (keymgr_dpe_scoreboard.sv:564) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hb6ee78cd388e3f74962c27164d76a5f4adf400c82acb8f1de1d12b1ca1e1fb6a1b8219cc5fa5b7944638d876adb964f6036c44e0dfa89566281a1713df91cd40 vs. act 'h0
  UVM_INFO @ 3077440689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---