ADC_CTRL Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.920s	5.927ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.680s	1.237ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.100s	540.968us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.968m	53.290ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.280s	1.139ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.050s	527.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.100s	540.968us	20	20	100.00
		adc_ctrl_csr_aliasing	5.280s	1.139ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.862m	505.738ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.747m	488.075ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.739m	494.424ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.425m	495.698ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	16.793m	502.208ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.041m	494.219ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.959m	513.059ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.153m	492.246ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.690s	5.184ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.778m	45.175ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.627m	142.093ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.356m	523.506ms	42	50	84.00
V2	alert_test	adc_ctrl_alert_test	1.720s	452.632us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	532.738us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.690s	424.283us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.690s	424.283us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.680s	1.237ms	5	5	100.00
		adc_ctrl_csr_rw	2.100s	540.968us	20	20	100.00
		adc_ctrl_csr_aliasing	5.280s	1.139ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.530s	4.728ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.680s	1.237ms	5	5	100.00
		adc_ctrl_csr_rw	2.100s	540.968us	20	20	100.00
		adc_ctrl_csr_aliasing	5.280s	1.139ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.530s	4.728ms	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	tl_intg_err	adc_ctrl_sec_cm	18.040s	7.342ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.400s	8.701ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.400s	8.701ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.876m	835.198ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			892	920	96.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.58	99.01	95.70	100.00	100.00	98.18	98.64	91.54

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 19 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 19 failures.
  - 4.adc_ctrl_stress_all_with_rand_reset.4119768988
    Line 335, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 4163142735 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 4163142735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 5.adc_ctrl_stress_all_with_rand_reset.619517956
    Line 404, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 384226463424 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 384226463424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 17 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 9 failures:

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

7.adc_ctrl_stress_all_with_rand_reset.3382500886
Line 381, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 258858316241 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 258858316241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 8 failures.

13.adc_ctrl_stress_all.162465856
Line 327, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 323017580620 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 323017580620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.adc_ctrl_stress_all.4139795453
Line 328, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 326592164549 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 326592164549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.