042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 15.120s | 6.077ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 3.530s | 1.186ms | 5 | 5 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 2.000s | 568.500us | 17 | 20 | 85.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 1.401m | 25.920ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 3.290s | 809.867us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 2.170s | 564.477us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 2.000s | 568.500us | 17 | 20 | 85.00 |
| adc_ctrl_csr_aliasing | 3.290s | 809.867us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 98 | 105 | 93.33 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 19.521m | 493.105ms | 50 | 50 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 19.512m | 498.121ms | 50 | 50 | 100.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 20.110m | 487.339ms | 50 | 50 | 100.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 19.778m | 486.966ms | 50 | 50 | 100.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 20.667m | 497.456ms | 50 | 50 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 20.235m | 491.354ms | 50 | 50 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 20.613m | 496.686ms | 50 | 50 | 100.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 20.016m | 495.413ms | 50 | 50 | 100.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 12.880s | 5.170ms | 50 | 50 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 1.808m | 45.171ms | 50 | 50 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 12.392m | 139.928ms | 50 | 50 | 100.00 |
| V2 | stress_all | adc_ctrl_stress_all | 27.644m | 693.285ms | 42 | 50 | 84.00 |
| V2 | alert_test | adc_ctrl_alert_test | 1.810s | 476.283us | 50 | 50 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 1.810s | 531.462us | 44 | 50 | 88.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 3.630s | 614.748us | 15 | 20 | 75.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 3.630s | 614.748us | 15 | 20 | 75.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 3.530s | 1.186ms | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 2.000s | 568.500us | 17 | 20 | 85.00 | ||
| adc_ctrl_csr_aliasing | 3.290s | 809.867us | 4 | 5 | 80.00 | ||
| adc_ctrl_same_csr_outstanding | 16.590s | 4.195ms | 17 | 20 | 85.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 3.530s | 1.186ms | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 2.000s | 568.500us | 17 | 20 | 85.00 | ||
| adc_ctrl_csr_aliasing | 3.290s | 809.867us | 4 | 5 | 80.00 | ||
| adc_ctrl_same_csr_outstanding | 16.590s | 4.195ms | 17 | 20 | 85.00 | ||
| V2 | TOTAL | 718 | 740 | 97.03 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 18.510s | 7.973ms | 5 | 5 | 100.00 |
| adc_ctrl_tl_intg_err | 22.420s | 8.332ms | 15 | 20 | 75.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 22.420s | 8.332ms | 15 | 20 | 75.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 17.723m | 1.072s | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 886 | 920 | 96.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 3 | 50.00 |
| V2 | 16 | 16 | 12 | 75.00 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.66 | 98.98 | 95.70 | 100.00 | 100.00 | 98.18 | 98.64 | 92.14 |
Exit reason: Error: User command failed Job returned non-zero exit code has 26 failures:
Test adc_ctrl_csr_aliasing has 1 failures.
0.adc_ctrl_csr_aliasing.8161484790365566277990410329312600600240270463361147182433063669756306143942
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/0.adc_ctrl_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410270406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.410270406
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test adc_ctrl_tl_intg_err has 5 failures.
1.adc_ctrl_tl_intg_err.50781239130651764356633435598924456679447241214171611937440449282830418675794
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/1.adc_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712583762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.3712583762
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.adc_ctrl_tl_intg_err.27903302462492616800120743571103229820171511092716163583871137863892033741365
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/2.adc_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661425717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.2661425717
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test adc_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
1.adc_ctrl_csr_mem_rw_with_rand_reset.36838843080409039421799403132633223861275316030867850347252387325450842193294
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497021838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1497021838
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
11.adc_ctrl_csr_mem_rw_with_rand_reset.39896753272063089521784308942924855585460135218351046009188001888949656931962
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757545594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2757545594
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test adc_ctrl_csr_rw has 3 failures.
2.adc_ctrl_csr_rw.105947071597702823280993647498385780767774252809900295930377268383031513390413
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest/run.log
[make]: simulate
cd /workspace/2.adc_ctrl_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744982861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2744982861
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:37 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
8.adc_ctrl_csr_rw.60016439976914767526049872799271002576336671702707862357880081009169234713799
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest/run.log
[make]: simulate
cd /workspace/8.adc_ctrl_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917036231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.917036231
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test adc_ctrl_tl_errors has 5 failures.
3.adc_ctrl_tl_errors.107227939461688070757144479953751412457793158430224119980240814210270358103240
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest/run.log
[make]: simulate
cd /workspace/3.adc_ctrl_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530253512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3530253512
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.adc_ctrl_tl_errors.85032687732833915663528598200337093484401227595507883028503046227626388490436
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest/run.log
[make]: simulate
cd /workspace/4.adc_ctrl_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417180356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3417180356
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
... and 2 more tests.
UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 8 failures:
5.adc_ctrl_stress_all.11633753428976732947067771928116025132262841052418469679904643117077298332373
Line 387, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 472634920025 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 472634920025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.adc_ctrl_stress_all.55070974765600984695602435593880684597589522823016736249164930220159546855307
Line 373, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 337351345908 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 337351345908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.