4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 0 | 50 | 0.00 | ||
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_both | adc_ctrl_filters_both | 0 | 50 | 0.00 | ||
| V2 | clock_gating | adc_ctrl_clock_gating | 0 | 50 | 0.00 | ||
| V2 | poweron_counter | adc_ctrl_poweron_counter | 0 | 50 | 0.00 | ||
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 0 | 50 | 0.00 | ||
| V2 | fsm_reset | adc_ctrl_fsm_reset | 0 | 50 | 0.00 | ||
| V2 | stress_all | adc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | adc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | adc_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 922 failures:
0.adc_ctrl_smoke.66952233584385584351642997707606080024867927672582497484808364084581823648475
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest/run.log
1.adc_ctrl_smoke.103888321300933987046976152939098240579500169577702737231224737035389330935555
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled.79194467541686246085278783881684688959981483552575384899336940443632238231511
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest/run.log
1.adc_ctrl_filters_polled.96696914452010856420000701598715308078259079623171667210813896301503669927678
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled_fixed.11315859168268342503204342435875572445284372630666551780042781891958628169075
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest/run.log
1.adc_ctrl_filters_polled_fixed.14807328924648055099827588765385192864669543238351466233368486181406034386646
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt.38645630920508220300111602633691149658177365367297781166262180926119102541747
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest/run.log
1.adc_ctrl_filters_interrupt.100522734309450356672687165532786485979629829033968033158579295466883875814985
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt_fixed.23085451677668234390366487441319705921888907785039417446905640186768731060556
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest/run.log
1.adc_ctrl_filters_interrupt_fixed.24183004371819421099630708533498502443051089685487597788012628595215489280642
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.