ADC_CTRL Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.540s	5.919ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.330s	659.364us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.120s	551.358us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.852m	25.993ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.430s	1.175ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.260s	581.549us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.120s	551.358us	20	20	100.00
		adc_ctrl_csr_aliasing	5.430s	1.175ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.260m	490.471ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.828m	486.497ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.976m	497.652ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.034m	498.030ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.104m	494.913ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	21.083m	495.890ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.667m	503.215ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	17.865m	491.961ms	49	50	98.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.570s	5.190ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.602m	48.566ms	49	50	98.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.970m	121.873ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.788m	632.807ms	42	50	84.00
V2	alert_test	adc_ctrl_alert_test	1.900s	526.651us	49	50	98.00
V2	intr_test	adc_ctrl_intr_test	1.810s	482.700us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.810s	471.830us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.810s	471.830us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.330s	659.364us	5	5	100.00
		adc_ctrl_csr_rw	2.120s	551.358us	20	20	100.00
		adc_ctrl_csr_aliasing	5.430s	1.175ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.450s	5.368ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.330s	659.364us	5	5	100.00
		adc_ctrl_csr_rw	2.120s	551.358us	20	20	100.00
		adc_ctrl_csr_aliasing	5.430s	1.175ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.450s	5.368ms	20	20	100.00
V2		TOTAL			729	740	98.51
V2S	tl_intg_err	adc_ctrl_sec_cm	18.480s	8.001ms	4	5	80.00
		adc_ctrl_tl_intg_err	22.560s	8.361ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.560s	8.361ms	20	20	100.00
V2S		TOTAL			24	25	96.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.529m	506.294ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			908	920	98.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	12	75.00
V2S	2	2	1	50.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	98.98	95.69	100.00	100.00	98.18	98.64	91.79

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 7 failures:
- Test adc_ctrl_stress_all has 7 failures.
  - 10.adc_ctrl_stress_all.109040410077082227328700220369594077170594411458237565621080170239061463523360
    Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 322945744786 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 322945744786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.adc_ctrl_stress_all.101011344119717465201901499080328352165896283659869566055831446837152023956619
    Line 361, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 323425584934 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 323425584934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job adc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test adc_ctrl_lowpower_counter has 1 failures.
  - 24.adc_ctrl_lowpower_counter.5770210463956590740733434302804334060415360462750424871903125847691969901576
    Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest/run.log
```
  Job ID: smart:8729a017-6252-4011-8d28-634d0a484a19
```
- Test adc_ctrl_clock_gating has 1 failures.
  - 45.adc_ctrl_clock_gating.26479989582435926941424870921767091315108580841078791143204034330387293308174
    Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest/run.log
```
  Job ID: smart:583f4488-8358-4613-9620-5b3d0779b8f8
```
Job adc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test adc_ctrl_sec_cm has 1 failures.
  - 3.adc_ctrl_sec_cm.39019685411526275425437036632446481887094003869176792022141187182515896964959
    Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest/run.log
```
  Job ID: smart:bc0b19d9-e1cc-4fd5-9543-dc5edac6fcbf
```
Job adc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test adc_ctrl_stress_all has 1 failures.
  - 45.adc_ctrl_stress_all.52480524371123199792949308271622899283819429254532910272990998002257682127298
    Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest/run.log
```
  Job ID: smart:80876e3b-a4b3-426d-a2ba-c9fad2ce8b6e
```
Job adc_ctrl-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test adc_ctrl_alert_test has 1 failures.
  - 45.adc_ctrl_alert_test.54564195484418067274649862222396884285659751647757762651478771900269890793909
    Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest/run.log
```
  Job ID: smart:09a68311-616e-4dba-805d-1a50b633a811
```

ADC_CTRL Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `796f9fb805`