ADC_CTRL Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.890s	5.841ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.210s	1.402ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.170s	572.751us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.220m	18.309ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.380s	851.869us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.940s	507.153us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.170s	572.751us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	851.869us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.380m	496.074ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.301m	497.861ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.437m	496.203ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.624m	488.450ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.168m	488.394ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.252m	498.909ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.433m	490.078ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.682m	497.462ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.570s	5.484ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.656m	40.652ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.394m	134.654ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	33.220m	460.046ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.760s	491.553us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.940s	524.475us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.530s	470.136us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.530s	470.136us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.210s	1.402ms	5	5	100.00
		adc_ctrl_csr_rw	2.170s	572.751us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	851.869us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.460s	3.982ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.210s	1.402ms	5	5	100.00
		adc_ctrl_csr_rw	2.170s	572.751us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	851.869us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.460s	3.982ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	20.350s	8.132ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.990s	8.264ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.990s	8.264ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.052m	694.720ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			914	920	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.55	98.98	95.70	100.00	100.00	98.18	98.64	91.37

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:
  • Test adc_ctrl_stress_all has 6 failures.

    • 3.adc_ctrl_stress_all.91897656029714313804192132948373262815463088208334944323750965769308660788401
      Line 467, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 368463845842 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 368463845842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.adc_ctrl_stress_all.26125201306217983329348061427056949035102920529965068658416659143630069163256
      Line 387, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 401311946461 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 401311946461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

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