ADC_CTRL Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.800s	5.903ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.020s	1.331ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.990s	489.508us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.990m	53.161ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.060s	956.600us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	528.247us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.990s	489.508us	20	20	100.00
		adc_ctrl_csr_aliasing	4.060s	956.600us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.384m	489.861ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.026m	487.554ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.017m	497.594ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.482m	500.021ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.381m	522.950ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.961m	500.324ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.688m	540.217ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.739m	494.935ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.530s	5.288ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.822m	46.683ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.832m	148.975ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.747m	601.374ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.870s	506.843us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.820s	464.126us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.310s	451.797us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.310s	451.797us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.020s	1.331ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	489.508us	20	20	100.00
		adc_ctrl_csr_aliasing	4.060s	956.600us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.700s	4.640ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.020s	1.331ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	489.508us	20	20	100.00
		adc_ctrl_csr_aliasing	4.060s	956.600us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.700s	4.640ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	19.550s	8.188ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.580s	8.412ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.580s	8.412ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.505m	1.069s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			915	920	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.47	98.98	95.70	100.00	100.00	98.18	98.64	90.77

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 5 failures:

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

3.adc_ctrl_stress_all_with_rand_reset.43050209328572826798326535733749001276951794415725446409504887137187358283254
Line 531, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 358098518909 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 358098518909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 4 failures.

3.adc_ctrl_stress_all.26629398910347311402816868278748638154658984678532296599188095089632262173443
Line 370, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 327828887599 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 327828887599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.adc_ctrl_stress_all.65251877883499460703571450773571939999850328024607799660800788814395967778115
Line 410, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 660759844268 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 660759844268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.