cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 16.250s | 5.932ms | 43 | 50 | 86.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 3.040s | 979.833us | 5 | 5 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 2.200s | 559.416us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 1.937m | 53.355ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 4.630s | 1.179ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 2.200s | 599.311us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 2.200s | 559.416us | 20 | 20 | 100.00 |
| adc_ctrl_csr_aliasing | 4.630s | 1.179ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 98 | 105 | 93.33 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 21.174m | 495.853ms | 45 | 50 | 90.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 19.791m | 489.977ms | 46 | 50 | 92.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 19.488m | 500.372ms | 45 | 50 | 90.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 19.448m | 499.102ms | 44 | 50 | 88.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 19.885m | 502.229ms | 43 | 50 | 86.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 20.229m | 484.318ms | 44 | 50 | 88.00 |
| V2 | filters_both | adc_ctrl_filters_both | 21.149m | 494.434ms | 45 | 50 | 90.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 18.747m | 484.917ms | 43 | 50 | 86.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 12.050s | 4.742ms | 44 | 50 | 88.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 1.661m | 45.049ms | 48 | 50 | 96.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 11.927m | 129.549ms | 46 | 50 | 92.00 |
| V2 | stress_all | adc_ctrl_stress_all | 27.706m | 597.828ms | 40 | 50 | 80.00 |
| V2 | alert_test | adc_ctrl_alert_test | 1.840s | 521.167us | 44 | 50 | 88.00 |
| V2 | intr_test | adc_ctrl_intr_test | 1.850s | 466.834us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 3.560s | 689.660us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 3.560s | 689.660us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 3.040s | 979.833us | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 2.200s | 559.416us | 20 | 20 | 100.00 | ||
| adc_ctrl_csr_aliasing | 4.630s | 1.179ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 14.770s | 5.050ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 3.040s | 979.833us | 5 | 5 | 100.00 |
| adc_ctrl_csr_rw | 2.200s | 559.416us | 20 | 20 | 100.00 | ||
| adc_ctrl_csr_aliasing | 4.630s | 1.179ms | 5 | 5 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 14.770s | 5.050ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 667 | 740 | 90.14 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 9.770s | 7.905ms | 5 | 5 | 100.00 |
| adc_ctrl_tl_intg_err | 22.520s | 7.940ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 22.520s | 7.940ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 6.507m | 291.318ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 833 | 920 | 90.54 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 16 | 16 | 3 | 18.75 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.46 | 98.98 | 95.70 | 100.00 | 100.00 | 98.18 | 98.64 | 90.72 |
Exit reason: Error: User command failed Job returned non-zero exit code has 80 failures:
Test adc_ctrl_clock_gating has 7 failures.
5.adc_ctrl_clock_gating.4700008855238376811502043771622283819821278814380074210792080281767523293925
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log
[make]: simulate
cd /workspace/5.adc_ctrl_clock_gating/latest && /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177538789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.2177538789
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.adc_ctrl_clock_gating.70797654017672644342839128007996247809668792203106259795472040769015182058143
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log
[make]: simulate
cd /workspace/9.adc_ctrl_clock_gating/latest && /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120882335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.3120882335
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Test adc_ctrl_filters_wakeup has 7 failures.
8.adc_ctrl_filters_wakeup.108691165421469599490379007883486902384052366287073910304253028413132736700644
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest/run.log
[make]: simulate
cd /workspace/8.adc_ctrl_filters_wakeup/latest && /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253950180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.4253950180
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
10.adc_ctrl_filters_wakeup.96054175436271174403211580036096469022550131652516609828062401914641973442719
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest/run.log
[make]: simulate
cd /workspace/10.adc_ctrl_filters_wakeup/latest && /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26409119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.26409119
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Test adc_ctrl_filters_both has 5 failures.
8.adc_ctrl_filters_both.45952034405499617254700910384230424660091560532250332097197413120732852199926
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest/run.log
[make]: simulate
cd /workspace/8.adc_ctrl_filters_both/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845123062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2845123062
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.adc_ctrl_filters_both.62051879167955909485159750719737183050877968983458982665864030315218433488167
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest/run.log
[make]: simulate
cd /workspace/9.adc_ctrl_filters_both/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998861607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1998861607
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test adc_ctrl_filters_interrupt_fixed has 6 failures.
9.adc_ctrl_filters_interrupt_fixed.45357084476366230540379461250327023284941671784255902495202906879581737691993
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest/run.log
[make]: simulate
cd /workspace/9.adc_ctrl_filters_interrupt_fixed/latest && /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781850457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.2781850457
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
10.adc_ctrl_filters_interrupt_fixed.78056727567228887141811993488147857242466409484351830964999742899332132264126
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest/run.log
[make]: simulate
cd /workspace/10.adc_ctrl_filters_interrupt_fixed/latest && /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264212158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.1264212158
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
Test adc_ctrl_lowpower_counter has 2 failures.
9.adc_ctrl_lowpower_counter.114867443252484992378063685745292599920711499933989092262335701267241026172001
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest/run.log
[make]: simulate
cd /workspace/9.adc_ctrl_lowpower_counter/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637332065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1637332065
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
15.adc_ctrl_lowpower_counter.87700669499465822522087234332607748402758409418228819555828036755555274049492
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest/run.log
[make]: simulate
cd /workspace/15.adc_ctrl_lowpower_counter/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606169556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3606169556
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:16 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 10 more tests.
UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:
0.adc_ctrl_stress_all.60086077098093362038755189484821993612746797209768933591839218291647415766932
Line 372, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 334847961876 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 334847961876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.adc_ctrl_stress_all.83769668311012556172226975718874686014799812570012091733744304018599316385668
Line 405, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 597828383799 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 597828383799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:99) [adc_ctrl_common_vseq] wait timeout occurred! has 1 failures:
42.adc_ctrl_stress_all_with_rand_reset.68469108634521120278420856838296785999013138052412398384361302150019597829280
Line 352, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 16624660834 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] wait timeout occurred!
UVM_INFO @ 16624660834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---