ADC_CTRL Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.970s	5.852ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.340s	1.137ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.010s	482.037us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.093m	52.890ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.220s	998.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.920s	501.660us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.010s	482.037us	20	20	100.00
		adc_ctrl_csr_aliasing	5.220s	998.354us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.741m	501.194ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.502m	499.643ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.651m	491.563ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.771m	485.874ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.518m	523.264ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.654m	496.325ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.442m	490.802ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.882m	491.367ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.230s	5.463ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.884m	46.085ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.007m	124.726ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.418m	659.360ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.770s	503.627us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.730s	456.158us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.520s	484.728us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.520s	484.728us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.340s	1.137ms	5	5	100.00
		adc_ctrl_csr_rw	2.010s	482.037us	20	20	100.00
		adc_ctrl_csr_aliasing	5.220s	998.354us	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.900s	4.047ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.340s	1.137ms	5	5	100.00
		adc_ctrl_csr_rw	2.010s	482.037us	20	20	100.00
		adc_ctrl_csr_aliasing	5.220s	998.354us	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.900s	4.047ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	18.360s	8.157ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.990s	8.339ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.990s	8.339ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.898m	427.577ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			914	920	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	98.98	95.69	100.00	100.00	98.18	98.64	91.07

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:
  • Test adc_ctrl_stress_all has 6 failures.

    • 3.adc_ctrl_stress_all.88486229742990609230102535613982988787106784603860350053290569810485222810297
      Line 374, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 341425612711 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 341425612711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.adc_ctrl_stress_all.25048052146045915357461442277953007367040706898867522110509982918499944572678
      Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 332706038716 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 332706038716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

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