ADC_CTRL Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.510s	5.861ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.130s	1.086ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.590s	486.076us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.185m	52.088ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.420s	1.057ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	552.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.590s	486.076us	20	20	100.00
		adc_ctrl_csr_aliasing	5.420s	1.057ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.383m	502.208ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.712m	497.747ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.027m	489.290ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.153m	492.124ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.507m	501.360ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.162m	494.379ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.718m	495.775ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.660m	504.896ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.880s	4.925ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.803m	45.067ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.223m	128.073ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.574m	670.478ms	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	1.900s	521.726us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.950s	513.277us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.320s	588.755us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.320s	588.755us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.130s	1.086ms	5	5	100.00
		adc_ctrl_csr_rw	1.590s	486.076us	20	20	100.00
		adc_ctrl_csr_aliasing	5.420s	1.057ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.820s	5.107ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.130s	1.086ms	5	5	100.00
		adc_ctrl_csr_rw	1.590s	486.076us	20	20	100.00
		adc_ctrl_csr_aliasing	5.420s	1.057ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.820s	5.107ms	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	tl_intg_err	adc_ctrl_sec_cm	10.280s	4.446ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.820s	7.816ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.820s	7.816ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.982m	867.837ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			915	920	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.54	98.98	95.69	100.00	100.00	98.18	98.64	91.27

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 5 failures:

Test adc_ctrl_stress_all has 3 failures.

3.adc_ctrl_stress_all.71693051500217048114047348272845176758185001074960373187790694796242935303046
Line 361, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 329368465491 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 329368465491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.adc_ctrl_stress_all.11058958816786017893851073675311459795544059623903478057469554630992930756875
Line 490, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 539164259555 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 539164259555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

34.adc_ctrl_stress_all_with_rand_reset.4956824825764614488815812250474441707207739819642514836011118685039473410751
Line 354, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 213219429539 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 213219429539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.adc_ctrl_stress_all_with_rand_reset.39249302936976017818570582542337430288275368368556332777455649048891210334139
Line 628, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 372784546789 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 372784546789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---