93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 0 | 50 | 0.00 | ||
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_both | adc_ctrl_filters_both | 0 | 50 | 0.00 | ||
| V2 | clock_gating | adc_ctrl_clock_gating | 0 | 50 | 0.00 | ||
| V2 | poweron_counter | adc_ctrl_poweron_counter | 0 | 50 | 0.00 | ||
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 0 | 50 | 0.00 | ||
| V2 | fsm_reset | adc_ctrl_fsm_reset | 0 | 50 | 0.00 | ||
| V2 | stress_all | adc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | adc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | adc_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 922 failures:
0.adc_ctrl_smoke.30877496653270621934329166171949298677221104630999210517352131238490373204307
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest/run.log
1.adc_ctrl_smoke.100601283356832413373290362357161889950819348404157708461699036530496678807467
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled.19161419505100546693062321783635993768036256156829551992941780992067000949761
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest/run.log
1.adc_ctrl_filters_polled.112359211343950872910859840513944536480517104795574698716888382488272247861722
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled_fixed.36484081987945812288519381090441957238292202134332629934150938625898750190139
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest/run.log
1.adc_ctrl_filters_polled_fixed.90925787564432054455624759233747152201813096926336214075364416761081434127543
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt.59094970344551502353449442358075998027133750291246696190456616194281130394705
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest/run.log
1.adc_ctrl_filters_interrupt.89716755085033858390407733533945885407080596653332757379175550076373108560873
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt_fixed.14714722091988569953508842377500803683226856645988595142937078044454139810206
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest/run.log
1.adc_ctrl_filters_interrupt_fixed.64599428833818670204623301742738427104413928645136824393361446190034196448613
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest/run.log
... and 48 more failures.
Job adc_ctrl-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/default/build.log
Job ID: smart:3e726d94-1ea3-47b1-af5e-b6abe878e1e8
Job adc_ctrl-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/cover_reg_top/build.log
Job ID: smart:3c5964ff-0f2c-4ea0-b8d4-07376d3c3e9c