ADC_CTRL Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.180s	6.054ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.050s	1.283ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.230s	555.491us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	58.210s	26.250ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.380s	1.114ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.620s	623.487us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.230s	555.491us	20	20	100.00
		adc_ctrl_csr_aliasing	5.380s	1.114ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.464m	483.500ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.513m	498.184ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.041m	485.398ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.341m	488.527ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.893m	489.798ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.655m	492.029ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.925m	489.985ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.510m	493.554ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.180s	5.404ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.647m	44.550ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.086m	130.415ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	37.364m	1.603s	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.870s	531.874us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.980s	504.243us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.640s	606.684us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.640s	606.684us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.050s	1.283ms	5	5	100.00
		adc_ctrl_csr_rw	2.230s	555.491us	20	20	100.00
		adc_ctrl_csr_aliasing	5.380s	1.114ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.350s	5.328ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.050s	1.283ms	5	5	100.00
		adc_ctrl_csr_rw	2.230s	555.491us	20	20	100.00
		adc_ctrl_csr_aliasing	5.380s	1.114ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.350s	5.328ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	17.190s	7.454ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.840s	8.079ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.840s	8.079ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.685m	793.675ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			913	920	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.58	98.98	95.69	100.00	100.00	98.18	98.64	91.59

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:
- Test adc_ctrl_stress_all has 4 failures.
  - 24.adc_ctrl_stress_all.109222221711179355181001026147047408542507766304018839181318538958433562364377
    Line 474, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 465424357551 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 465424357551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.adc_ctrl_stress_all.98255827205912945028838348847226404469158678502741219713930837401184193121870
    Line 361, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 325568198307 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 325568198307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 2 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 8.adc_ctrl_stress_all_with_rand_reset.62899263721083871143627764201892990604721901445281401043863136881826478117286
    Line 455, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 54722644884 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 168 [0xa8]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 54722644884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.adc_ctrl_stress_all_with_rand_reset.25187067907935346710140268851995954229392135427007044662076157995148563349264
    Line 678, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 597355582022 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 65 [0x41]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 597355582022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:714) [adc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.adc_ctrl_stress_all_with_rand_reset.70150282137969857511040826663845975151800422762229888941047359831469973986195
    Line 473, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 279554783904 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 279554783904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8faf04697a`