ADC_CTRL Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.390s	5.953ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.580s	766.952us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.280s	523.881us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.697m	23.760ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.060s	911.244us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.180s	527.150us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.280s	523.881us	20	20	100.00
		adc_ctrl_csr_aliasing	4.060s	911.244us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.739m	498.227ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.222m	500.847ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.201m	487.342ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.237m	507.663ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.647m	524.202ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.132m	499.850ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.726m	498.603ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.929m	503.448ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.320s	5.556ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.709m	47.954ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.024m	126.145ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	31.091m	476.699ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.870s	515.457us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.950s	535.257us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.190s	548.100us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.190s	548.100us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.580s	766.952us	5	5	100.00
		adc_ctrl_csr_rw	2.280s	523.881us	20	20	100.00
		adc_ctrl_csr_aliasing	4.060s	911.244us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.760s	4.746ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.580s	766.952us	5	5	100.00
		adc_ctrl_csr_rw	2.280s	523.881us	20	20	100.00
		adc_ctrl_csr_aliasing	4.060s	911.244us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.760s	4.746ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	10.990s	4.324ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.220s	8.543ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.220s	8.543ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.954m	324.113ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			914	920	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	99.01	95.74	100.00	100.00	98.24	98.64	91.52

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 5 failures:

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

20.adc_ctrl_stress_all_with_rand_reset.77265380740959858489313043500502911022330332845175439457002020394613630472536
Line 578, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 510226741272 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 510226741272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 4 failures.

30.adc_ctrl_stress_all.12583535334113463435086599271538748117645992141598457772242381907730419576552
Line 474, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 377181587737 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 377181587737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.adc_ctrl_stress_all.114211598802981263698372439168326955996413614483732771480834702637918336511581
Line 467, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 368987949573 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 368987949573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.adc_ctrl_stress_all_with_rand_reset.58045745576812343200540120069810015448641627542042633494493499622912883498806
    Line 458, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120271512050 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 101 [0x65]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 120271512050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```