ADC_CTRL Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.380s	5.720ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.890s	992.645us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.130s	571.078us	19	20	95.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.662m	43.523ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.600s	731.794us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.200s	593.876us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.130s	571.078us	19	20	95.00
		adc_ctrl_csr_aliasing	3.600s	731.794us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	filters_polled	adc_ctrl_filters_polled	20.753m	496.586ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.813m	493.026ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.547m	493.419ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.338m	499.973ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.773m	571.657ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.203m	600.767ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.087m	540.324ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.559m	524.670ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.010s	4.961ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.810m	46.525ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.095m	128.317ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.151m	586.497ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	525.505us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.940s	517.661us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.630s	535.747us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.630s	535.747us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.890s	992.645us	5	5	100.00
		adc_ctrl_csr_rw	2.130s	571.078us	19	20	95.00
		adc_ctrl_csr_aliasing	3.600s	731.794us	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.180s	4.460ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.890s	992.645us	5	5	100.00
		adc_ctrl_csr_rw	2.130s	571.078us	19	20	95.00
		adc_ctrl_csr_aliasing	3.600s	731.794us	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.180s	4.460ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	19.230s	8.232ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.020s	8.661ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.020s	8.661ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.039m	441.040ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.37

Failure Buckets

Offending '(cfg_lp_sample_cnt_i > '0)' has 1 failures:
- Test adc_ctrl_csr_rw has 1 failures.
  - 14.adc_ctrl_csr_rw.19141914526341871441471732898196248292535394109959538824053455043795730686771
    Line 333, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest/run.log
```
      Offending '(cfg_lp_sample_cnt_i > '0)'
  UVM_ERROR @ 544590502 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
  UVM_INFO @ 544590502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.adc_ctrl_stress_all_with_rand_reset.87085014737008404289707549626394194659853282876704231987612271019958812856601
    Line 474, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100005008296 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 100005008296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ae68723071`