ADC_CTRL Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.640s	6.129ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.570s	1.268ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.110s	541.695us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.675m	40.702ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.840s	774.218us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.150s	519.968us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.110s	541.695us	20	20	100.00
		adc_ctrl_csr_aliasing	4.840s	774.218us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.360m	505.401ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	16.617m	477.798ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	18.369m	495.016ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.650m	500.771ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.527m	640.040ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.320m	617.365ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.369m	535.031ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.982m	497.661ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.750s	5.325ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.808m	46.099ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.273m	133.960ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.476m	581.332ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.770s	450.149us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.890s	507.921us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.110s	639.326us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.110s	639.326us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.570s	1.268ms	5	5	100.00
		adc_ctrl_csr_rw	2.110s	541.695us	20	20	100.00
		adc_ctrl_csr_aliasing	4.840s	774.218us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.710s	4.574ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.570s	1.268ms	5	5	100.00
		adc_ctrl_csr_rw	2.110s	541.695us	20	20	100.00
		adc_ctrl_csr_aliasing	4.840s	774.218us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.710s	4.574ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	20.030s	7.535ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.090s	8.580ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.090s	8.580ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	20.295m	1.417s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.85	99.07	96.67	100.00	100.00	98.83	98.33	92.09

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.adc_ctrl_stress_all_with_rand_reset.110844488210082262840453708043890298338919309071664686676797517143824368125441
    Line 373, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41264997955 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 41264997955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `41bc3e0c7f`