ADC_CTRL Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.850s	6.110ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.040s	1.150ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.070s	512.378us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	27.880s	18.370ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.190s	1.271ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.320s	534.930us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.070s	512.378us	20	20	100.00
		adc_ctrl_csr_aliasing	5.190s	1.271ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	17.927m	490.232ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.949m	484.732ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.611m	498.570ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.859m	495.238ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.848m	588.231ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.600m	609.431ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.618m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	18.817m	531.464ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.480s	5.758ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.753m	45.366ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.544m	131.012ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.752m	660.578ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.790s	502.827us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.910s	511.592us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.970s	633.818us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.970s	633.818us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.040s	1.150ms	5	5	100.00
		adc_ctrl_csr_rw	2.070s	512.378us	20	20	100.00
		adc_ctrl_csr_aliasing	5.190s	1.271ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.840s	4.448ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.040s	1.150ms	5	5	100.00
		adc_ctrl_csr_rw	2.070s	512.378us	20	20	100.00
		adc_ctrl_csr_aliasing	5.190s	1.271ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.840s	4.448ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	20.880s	8.372ms	5	5	100.00
		adc_ctrl_tl_intg_err	19.990s	8.197ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	19.990s	8.197ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.046m	575.017ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.29

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 24.adc_ctrl_filters_both.30497898586999099636995039861866209024053010485657481324439960273934585594865
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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