ADC_CTRL Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.340s 5.984ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.330s 1.267ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.000s 494.726us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.850m 51.563ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.100s 1.203ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.410s 638.840us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.000s 494.726us 20 20 100.00
adc_ctrl_csr_aliasing 5.100s 1.203ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.535m 500.666ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.097m 497.342ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.695m 491.715ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 21.668m 510.708ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 26.286m 653.949ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.564m 594.634ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.482m 517.456ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 21.216m 526.888ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 15.420s 5.514ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.734m 43.454ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.765m 143.096ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 22.461m 539.528ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.880s 527.952us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.850s 521.807us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.760s 458.961us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.760s 458.961us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.330s 1.267ms 5 5 100.00
adc_ctrl_csr_rw 2.000s 494.726us 20 20 100.00
adc_ctrl_csr_aliasing 5.100s 1.203ms 5 5 100.00
adc_ctrl_same_csr_outstanding 15.240s 4.359ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.330s 1.267ms 5 5 100.00
adc_ctrl_csr_rw 2.000s 494.726us 20 20 100.00
adc_ctrl_csr_aliasing 5.100s 1.203ms 5 5 100.00
adc_ctrl_same_csr_outstanding 15.240s 4.359ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 16.820s 7.445ms 5 5 100.00
adc_ctrl_tl_intg_err 22.840s 8.331ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.840s 8.331ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 15.154m 512.747ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.66

Past Results