ADC_CTRL Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.540s	6.012ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.700s	779.281us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.770s	436.391us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.843m	53.469ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.800s	1.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.330s	609.284us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.770s	436.391us	20	20	100.00
		adc_ctrl_csr_aliasing	2.800s	1.009ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.691m	496.901ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.927m	496.746ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.680m	492.274ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.547m	495.513ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.020m	668.561ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.866m	600.553ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.644m	533.469ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.230m	579.049ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.460s	5.368ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.804m	45.823ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.175m	135.965ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.559m	649.798ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.790s	449.000us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	487.223us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.220s	523.563us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.220s	523.563us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.700s	779.281us	5	5	100.00
		adc_ctrl_csr_rw	1.770s	436.391us	20	20	100.00
		adc_ctrl_csr_aliasing	2.800s	1.009ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.280s	4.389ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.700s	779.281us	5	5	100.00
		adc_ctrl_csr_rw	1.770s	436.391us	20	20	100.00
		adc_ctrl_csr_aliasing	2.800s	1.009ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.280s	4.389ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	20.710s	8.564ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.730s	8.306ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.730s	8.306ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.273m	178.117ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			916	920	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.07	96.67	100.00	100.00	98.83	98.33	90.77

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 36.adc_ctrl_filters_both.93166089843533676539404213527706876675366603006389492158042761020011497599496
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.adc_ctrl_filters_both.9707336777461298058923114506480957154038620403736623107049944710761740307115
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.adc_ctrl_stress_all_with_rand_reset.69253070621163177846048044936561018805245060912522486153122050136959665057601
    Line 403, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23462747509 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 23462747509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.adc_ctrl_stress_all_with_rand_reset.43506806204578985979522736074522947211261483918907405423328266683401599346955
    Line 455, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89672851508 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 33 [0x21]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 89672851508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d3942ca074`