ADC_CTRL Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.990s	5.921ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.920s	1.370ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.110s	548.873us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	51.710s	42.304ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.670s	819.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.280s	570.386us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.110s	548.873us	20	20	100.00
		adc_ctrl_csr_aliasing	4.670s	819.811us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.969m	500.887ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.914m	493.289ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.474m	486.363ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.136m	493.311ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.910m	569.755ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.358m	596.844ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.560m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.477m	492.772ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.560s	5.938ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.764m	46.866ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.225m	133.448ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	59.891m	1.546s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.950s	476.705us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.780s	508.079us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.300s	533.603us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.300s	533.603us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.920s	1.370ms	5	5	100.00
		adc_ctrl_csr_rw	2.110s	548.873us	20	20	100.00
		adc_ctrl_csr_aliasing	4.670s	819.811us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.900s	4.543ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.920s	1.370ms	5	5	100.00
		adc_ctrl_csr_rw	2.110s	548.873us	20	20	100.00
		adc_ctrl_csr_aliasing	4.670s	819.811us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.900s	4.543ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.300s	8.273ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.100s	8.437ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.100s	8.437ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.313m	946.217ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 33.adc_ctrl_filters_both.114653095558402955277548728616333606389117281157972553696672239088975675957843
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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