ADC_CTRL Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.900s 5.907ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.350s 1.207ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.030s 523.712us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.679m 46.124ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 6.960s 1.314ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.270s 617.860us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.030s 523.712us 20 20 100.00
adc_ctrl_csr_aliasing 6.960s 1.314ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.744m 497.338ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.400m 483.919ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 21.012m 502.379ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.660m 496.544ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.984m 568.636ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.927m 609.162ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 24.285m 600.000ms 47 50 94.00
V2 clock_gating adc_ctrl_clock_gating 18.397m 572.211ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.770s 5.431ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.948m 46.228ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.069m 136.605ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 46.456m 1.105s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.860s 526.425us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.960s 521.457us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.580s 961.936us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.580s 961.936us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.350s 1.207ms 5 5 100.00
adc_ctrl_csr_rw 2.030s 523.712us 20 20 100.00
adc_ctrl_csr_aliasing 6.960s 1.314ms 5 5 100.00
adc_ctrl_same_csr_outstanding 17.530s 4.451ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.350s 1.207ms 5 5 100.00
adc_ctrl_csr_rw 2.030s 523.712us 20 20 100.00
adc_ctrl_csr_aliasing 6.960s 1.314ms 5 5 100.00
adc_ctrl_same_csr_outstanding 17.530s 4.451ms 20 20 100.00
V2 TOTAL 737 740 99.59
V2S tl_intg_err adc_ctrl_sec_cm 17.850s 7.570ms 5 5 100.00
adc_ctrl_tl_intg_err 22.610s 8.089ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.610s 8.089ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 10.471m 298.184ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 917 920 99.67

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 15 93.75
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92

Failure Buckets

Past Results