ADC_CTRL Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.130s	6.014ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.470s	1.215ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.210s	550.872us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.835m	28.877ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.160s	771.629us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.050s	499.988us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.210s	550.872us	20	20	100.00
		adc_ctrl_csr_aliasing	4.160s	771.629us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.199m	500.551ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.176m	488.799ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.015m	493.248ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.212m	504.337ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.862m	560.395ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.929m	594.330ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.386m	528.098ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.435m	505.078ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.230s	5.418ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.685m	40.633ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.546m	112.894ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	19.659m	3.336s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.920s	533.450us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	501.880us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.170s	471.690us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.170s	471.690us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.470s	1.215ms	5	5	100.00
		adc_ctrl_csr_rw	2.210s	550.872us	20	20	100.00
		adc_ctrl_csr_aliasing	4.160s	771.629us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.890s	5.258ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.470s	1.215ms	5	5	100.00
		adc_ctrl_csr_rw	2.210s	550.872us	20	20	100.00
		adc_ctrl_csr_aliasing	4.160s	771.629us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.890s	5.258ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	17.720s	8.018ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.380s	8.653ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.380s	8.653ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.594m	226.306ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.07	96.67	100.00	100.00	98.83	98.33	90.97

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 44.adc_ctrl_filters_both.61933305499532273656027448807113196129167291819249036704149764539319362392869
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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