ADC_CTRL Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.740s	6.078ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.840s	1.234ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.130s	560.312us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.531m	38.440ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.910s	1.165ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.250s	468.153us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.130s	560.312us	20	20	100.00
		adc_ctrl_csr_aliasing	6.910s	1.165ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.845m	504.235ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.619m	495.409ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.029m	496.422ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.340m	493.240ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.163m	536.009ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.336m	615.186ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.294m	577.482ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.120m	515.157ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.550s	5.276ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.706m	41.467ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.690m	133.587ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	49.390m	1.166s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.880s	516.591us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	513.579us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.600s	720.186us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.600s	720.186us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.840s	1.234ms	5	5	100.00
		adc_ctrl_csr_rw	2.130s	560.312us	20	20	100.00
		adc_ctrl_csr_aliasing	6.910s	1.165ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.080s	5.105ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.840s	1.234ms	5	5	100.00
		adc_ctrl_csr_rw	2.130s	560.312us	20	20	100.00
		adc_ctrl_csr_aliasing	6.910s	1.165ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.080s	5.105ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.430s	7.715ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.330s	8.005ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.330s	8.005ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	16.030m	522.785ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.24

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 27.adc_ctrl_filters_both.111221881438911032546205568755619106382974186262027009330729981758023502684676
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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