ADC_CTRL Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.460s	6.154ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.130s	1.118ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.100s	505.864us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.473m	26.293ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.020s	1.203ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.270s	598.642us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.100s	505.864us	20	20	100.00
		adc_ctrl_csr_aliasing	3.020s	1.203ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.644m	493.440ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.622m	495.507ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.145m	491.148ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.620m	488.103ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.985m	644.802ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.939m	611.054ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.508m	529.112ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	18.668m	514.398ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.220s	5.303ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.872m	44.212ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.581m	137.196ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.416m	487.670ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.840s	484.128us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	509.415us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.830s	426.088us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.830s	426.088us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.130s	1.118ms	5	5	100.00
		adc_ctrl_csr_rw	2.100s	505.864us	20	20	100.00
		adc_ctrl_csr_aliasing	3.020s	1.203ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.470s	4.242ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.130s	1.118ms	5	5	100.00
		adc_ctrl_csr_rw	2.100s	505.864us	20	20	100.00
		adc_ctrl_csr_aliasing	3.020s	1.203ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.470s	4.242ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	17.460s	8.317ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.820s	8.537ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.820s	8.537ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.177m	511.895ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	99.07	96.62	100.00	100.00	98.83	98.33	90.79

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 8.adc_ctrl_filters_both.35870021268488860678431404556564628598706594684597500367328241750233681306485
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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