ADC_CTRL Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.510s	5.772ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.100s	975.804us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.100s	548.923us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	28.280s	26.538ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.340s	1.372ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.200s	461.865us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.100s	548.923us	20	20	100.00
		adc_ctrl_csr_aliasing	4.340s	1.372ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.930m	483.435ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.740m	496.897ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.019m	490.553ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.630m	505.524ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.072m	673.053ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.253m	617.290ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.330m	527.402ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	16.256m	518.162ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.700s	5.364ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.508m	36.847ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.758m	145.208ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.776m	659.424ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.910s	524.825us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.900s	478.743us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.540s	517.935us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.540s	517.935us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.100s	975.804us	5	5	100.00
		adc_ctrl_csr_rw	2.100s	548.923us	20	20	100.00
		adc_ctrl_csr_aliasing	4.340s	1.372ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.090s	4.055ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.100s	975.804us	5	5	100.00
		adc_ctrl_csr_rw	2.100s	548.923us	20	20	100.00
		adc_ctrl_csr_aliasing	4.340s	1.372ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.090s	4.055ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	11.620s	4.534ms	5	5	100.00
		adc_ctrl_tl_intg_err	25.280s	9.002ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	25.280s	9.002ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.936m	682.475ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.adc_ctrl_stress_all_with_rand_reset.84871595008160845994400105827206699842842694989400850127315419800931431237807
    Line 385, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9554312535 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9554312535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 32.adc_ctrl_filters_both.79117135442369490521809461196696315392170968169071434553782273180680388284920
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9656691e03`