ADC_CTRL Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.180s 5.830ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.650s 1.238ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.980s 534.230us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.808m 27.108ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.360s 1.081ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.290s 611.874us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.980s 534.230us 20 20 100.00
adc_ctrl_csr_aliasing 4.360s 1.081ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.388m 488.709ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.225m 488.821ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.506m 491.814ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.168m 488.833ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.488m 552.613ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.228m 591.717ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.777m 504.004ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 22.785m 588.842ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.980s 5.537ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.868m 46.516ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.809m 148.529ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 33.521m 595.737ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.810s 495.000us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.840s 472.766us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 4.180s 557.346us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 4.180s 557.346us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.650s 1.238ms 5 5 100.00
adc_ctrl_csr_rw 1.980s 534.230us 20 20 100.00
adc_ctrl_csr_aliasing 4.360s 1.081ms 5 5 100.00
adc_ctrl_same_csr_outstanding 16.400s 4.789ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.650s 1.238ms 5 5 100.00
adc_ctrl_csr_rw 1.980s 534.230us 20 20 100.00
adc_ctrl_csr_aliasing 4.360s 1.081ms 5 5 100.00
adc_ctrl_same_csr_outstanding 16.400s 4.789ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 11.710s 4.729ms 5 5 100.00
adc_ctrl_tl_intg_err 23.570s 9.047ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 23.570s 9.047ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 10.209m 592.825ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.46

Past Results