ADC_CTRL Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.310s	6.079ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.240s	1.045ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.150s	566.928us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.276m	27.096ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.380s	886.615us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.530s	625.906us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.150s	566.928us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	886.615us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.220m	500.003ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.088m	487.559ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.279m	502.792ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.378m	487.895ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.902m	563.692ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.779m	605.558ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.600m	525.025ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.538m	604.627ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.860s	4.857ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.850m	47.514ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.740m	126.303ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	29.831m	601.615ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.900s	531.020us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.840s	522.905us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.440s	459.098us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.440s	459.098us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.240s	1.045ms	5	5	100.00
		adc_ctrl_csr_rw	2.150s	566.928us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	886.615us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.230s	4.596ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.240s	1.045ms	5	5	100.00
		adc_ctrl_csr_rw	2.150s	566.928us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	886.615us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.230s	4.596ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	11.000s	4.274ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.090s	9.047ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.090s	9.047ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.559m	468.329ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.17

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 0.adc_ctrl_filters_both.16209696034984713806060967305308159137099999560696889950574429355720742036745
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`