ADC_CTRL Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.240s	5.756ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.620s	1.165ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.800s	476.904us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.416m	24.559ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.400s	1.036ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.380s	617.088us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.800s	476.904us	20	20	100.00
		adc_ctrl_csr_aliasing	4.400s	1.036ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.413m	496.152ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.437m	496.174ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.525m	488.333ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.430m	487.330ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.741m	545.708ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.393m	610.921ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.848m	527.939ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.029m	521.660ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.950s	5.167ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.879m	45.991ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.880m	131.337ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.584h	2.854s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.790s	482.353us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.810s	480.204us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.250s	545.499us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.250s	545.499us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.620s	1.165ms	5	5	100.00
		adc_ctrl_csr_rw	1.800s	476.904us	20	20	100.00
		adc_ctrl_csr_aliasing	4.400s	1.036ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.570s	3.594ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.620s	1.165ms	5	5	100.00
		adc_ctrl_csr_rw	1.800s	476.904us	20	20	100.00
		adc_ctrl_csr_aliasing	4.400s	1.036ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.570s	3.594ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	10.210s	4.238ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.230s	8.550ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.230s	8.550ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.707m	495.138ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.86	99.07	96.67	100.00	100.00	98.83	98.33	92.11

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 39.adc_ctrl_filters_both.29289779487770956570257019194221198278206710274857549778821331440403575854146
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`