ADC_CTRL Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.640s 5.969ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.570s 716.696us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.930s 522.949us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.151m 52.513ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.720s 1.299ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.160s 515.873us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.930s 522.949us 20 20 100.00
adc_ctrl_csr_aliasing 5.720s 1.299ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 20.469m 501.434ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 17.104m 489.255ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.082m 491.057ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.814m 488.285ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 23.510m 622.971ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.463m 592.428ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 21.785m 542.556ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.963m 540.763ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.170s 5.438ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.866m 45.886ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.831m 125.034ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 28.414m 625.471ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.870s 529.131us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.880s 529.241us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.860s 497.925us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.860s 497.925us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.570s 716.696us 5 5 100.00
adc_ctrl_csr_rw 1.930s 522.949us 20 20 100.00
adc_ctrl_csr_aliasing 5.720s 1.299ms 5 5 100.00
adc_ctrl_same_csr_outstanding 13.240s 4.195ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.570s 716.696us 5 5 100.00
adc_ctrl_csr_rw 1.930s 522.949us 20 20 100.00
adc_ctrl_csr_aliasing 5.720s 1.299ms 5 5 100.00
adc_ctrl_same_csr_outstanding 13.240s 4.195ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 10.710s 4.504ms 5 5 100.00
adc_ctrl_tl_intg_err 19.760s 8.727ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 19.760s 8.727ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 11.802m 332.957ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.61

Past Results