ADC_CTRL Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.260s 5.838ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.080s 1.094ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.980s 506.622us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.033m 52.778ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.620s 963.026us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.080s 564.158us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.980s 506.622us 20 20 100.00
adc_ctrl_csr_aliasing 4.620s 963.026us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 20.214m 498.715ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.264m 495.912ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.369m 496.812ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.994m 496.067ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 24.587m 645.721ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.759m 604.177ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.232m 539.401ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.974m 622.327ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.820s 5.332ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.790m 43.580ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.337m 143.827ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 1.181h 1.789s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.830s 520.067us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.920s 532.491us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.490s 394.895us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.490s 394.895us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.080s 1.094ms 5 5 100.00
adc_ctrl_csr_rw 1.980s 506.622us 20 20 100.00
adc_ctrl_csr_aliasing 4.620s 963.026us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.530s 4.387ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.080s 1.094ms 5 5 100.00
adc_ctrl_csr_rw 1.980s 506.622us 20 20 100.00
adc_ctrl_csr_aliasing 4.620s 963.026us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.530s 4.387ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 10.820s 4.350ms 5 5 100.00
adc_ctrl_tl_intg_err 22.470s 8.278ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.470s 8.278ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 13.209m 3.463s 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 917 920 99.67

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.66 99.07 96.62 100.00 100.00 98.83 98.33 90.77

Failure Buckets

Past Results