ADC_CTRL Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.340s	6.078ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.660s	934.826us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.670s	391.299us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.687m	20.620ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.690s	1.089ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.940s	468.925us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.670s	391.299us	20	20	100.00
		adc_ctrl_csr_aliasing	4.690s	1.089ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.689m	497.711ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.412m	500.728ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.851m	496.716ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.676m	492.157ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.157m	672.009ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.251m	607.154ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.470m	559.266ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.564m	518.402ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.540s	5.156ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.013m	48.703ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.918m	140.669ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.053h	1.462s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.720s	464.527us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	532.592us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.740s	626.732us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.740s	626.732us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.660s	934.826us	5	5	100.00
		adc_ctrl_csr_rw	1.670s	391.299us	20	20	100.00
		adc_ctrl_csr_aliasing	4.690s	1.089ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.430s	3.990ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.660s	934.826us	5	5	100.00
		adc_ctrl_csr_rw	1.670s	391.299us	20	20	100.00
		adc_ctrl_csr_aliasing	4.690s	1.089ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.430s	3.990ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	17.090s	7.797ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.330s	8.415ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.330s	8.415ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.508m	1.046s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.32

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.adc_ctrl_stress_all_with_rand_reset.60804015542928391715258425012583464885483647692404738198391992391237127018756
    Line 413, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56769801688 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 56769801688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0bfa990ddc`