ADC_CTRL Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.400s 6.150ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.490s 1.218ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.170s 548.184us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.658m 49.014ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.460s 1.205ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.260s 506.890us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.170s 548.184us 20 20 100.00
adc_ctrl_csr_aliasing 5.460s 1.205ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.352m 491.830ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.191m 495.649ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.061m 488.253ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.512m 492.540ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.651m 539.632ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.477m 591.284ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.812m 537.223ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.349m 521.307ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.630s 5.594ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.863m 44.688ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.302m 129.970ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 33.180m 567.151ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.870s 526.776us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.750s 513.050us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.990s 638.564us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.990s 638.564us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.490s 1.218ms 5 5 100.00
adc_ctrl_csr_rw 2.170s 548.184us 20 20 100.00
adc_ctrl_csr_aliasing 5.460s 1.205ms 5 5 100.00
adc_ctrl_same_csr_outstanding 14.530s 4.182ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.490s 1.218ms 5 5 100.00
adc_ctrl_csr_rw 2.170s 548.184us 20 20 100.00
adc_ctrl_csr_aliasing 5.460s 1.205ms 5 5 100.00
adc_ctrl_same_csr_outstanding 14.530s 4.182ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 21.820s 8.604ms 5 5 100.00
adc_ctrl_tl_intg_err 21.440s 8.200ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 21.440s 8.200ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 8.715m 206.802ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14

Past Results