ADC_CTRL Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.100s 6.106ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.770s 1.277ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.100s 533.763us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.881m 53.060ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.060s 1.298ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.270s 546.595us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.100s 533.763us 20 20 100.00
adc_ctrl_csr_aliasing 5.060s 1.298ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 20.058m 495.241ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.640m 497.767ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.572m 488.241ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.971m 489.292ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 23.445m 570.913ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.504m 622.042ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.065m 534.474ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.648m 600.152ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.420s 5.488ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.625m 42.037ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.916m 137.985ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 29.819m 709.542ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.700s 454.688us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.820s 507.295us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.540s 547.514us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.540s 547.514us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.770s 1.277ms 5 5 100.00
adc_ctrl_csr_rw 2.100s 533.763us 20 20 100.00
adc_ctrl_csr_aliasing 5.060s 1.298ms 5 5 100.00
adc_ctrl_same_csr_outstanding 15.690s 5.322ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.770s 1.277ms 5 5 100.00
adc_ctrl_csr_rw 2.100s 533.763us 20 20 100.00
adc_ctrl_csr_aliasing 5.060s 1.298ms 5 5 100.00
adc_ctrl_same_csr_outstanding 15.690s 5.322ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 18.700s 8.334ms 5 5 100.00
adc_ctrl_tl_intg_err 22.190s 8.531ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.190s 8.531ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 9.627m 500.972ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.54

Past Results