ADC_CTRL Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.480s	5.973ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.220s	1.108ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.990s	467.986us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.882m	27.102ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.440s	1.210ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.200s	515.739us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.990s	467.986us	20	20	100.00
		adc_ctrl_csr_aliasing	3.440s	1.210ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.888m	498.650ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.372m	496.590ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.275m	487.464ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.941m	488.549ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.645m	696.248ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.026m	603.125ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.678m	543.185ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.652m	557.718ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.350s	5.174ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.714m	46.347ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.615m	123.430ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.586m	463.137ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.810s	518.847us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.810s	524.920us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.530s	431.587us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.530s	431.587us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.220s	1.108ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	467.986us	20	20	100.00
		adc_ctrl_csr_aliasing	3.440s	1.210ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.990s	4.492ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.220s	1.108ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	467.986us	20	20	100.00
		adc_ctrl_csr_aliasing	3.440s	1.210ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.990s	4.492ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	20.250s	8.352ms	5	5	100.00
		adc_ctrl_tl_intg_err	19.750s	8.099ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	19.750s	8.099ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.092m	442.999ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.14

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 48.adc_ctrl_stress_all_with_rand_reset.44318701183036672390105122772095621966262411971338502869801151061918937481858
    Line 376, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20597084926 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 179 [0xb3]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 20597084926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `39f3866b56`