ADC_CTRL Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	14.830s	5.978ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.040s	960.830us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.870s	495.747us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.827m	50.980ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.520s	1.192ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.370s	560.720us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.870s	495.747us	20	20	100.00
		adc_ctrl_csr_aliasing	4.520s	1.192ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.334m	496.859ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.501m	502.175ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.937m	501.115ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.639m	496.289ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.187m	546.970ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.343m	590.718ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.414m	526.163ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.344m	529.872ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.010s	4.643ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.639m	44.305ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.752m	131.048ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	30.000m	657.176ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.870s	525.588us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.760s	502.019us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.200s	559.307us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.200s	559.307us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.040s	960.830us	5	5	100.00
		adc_ctrl_csr_rw	1.870s	495.747us	20	20	100.00
		adc_ctrl_csr_aliasing	4.520s	1.192ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.930s	4.338ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.040s	960.830us	5	5	100.00
		adc_ctrl_csr_rw	1.870s	495.747us	20	20	100.00
		adc_ctrl_csr_aliasing	4.520s	1.192ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.930s	4.338ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	20.360s	8.245ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.670s	9.021ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.670s	9.021ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.602m	4.178s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	99.07	96.67	100.00	100.00	98.83	98.33	90.59

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 21.adc_ctrl_filters_both.113614804987020379307481619276925016010058881847106134209982263517520445447362
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.adc_ctrl_stress_all_with_rand_reset.51238125679513178303509540297561647107041643758467168729163641442387932098754
    Line 417, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 33579173669 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 33579173669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `fdfa12db04`