ADC_CTRL Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.950s	6.039ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.350s	1.235ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.870s	507.138us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	47.340s	51.532ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.700s	1.262ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.150s	540.231us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.870s	507.138us	20	20	100.00
		adc_ctrl_csr_aliasing	4.700s	1.262ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.230m	493.935ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.538m	484.553ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.464m	486.203ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.747m	492.984ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	27.706m	727.730ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.753m	599.568ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.639m	556.205ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.992m	542.305ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.870s	5.425ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.837m	45.137ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.563m	134.996ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	29.289m	697.172ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	526.108us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.680s	456.365us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.780s	596.980us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.780s	596.980us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.350s	1.235ms	5	5	100.00
		adc_ctrl_csr_rw	1.870s	507.138us	20	20	100.00
		adc_ctrl_csr_aliasing	4.700s	1.262ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.290s	4.212ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.350s	1.235ms	5	5	100.00
		adc_ctrl_csr_rw	1.870s	507.138us	20	20	100.00
		adc_ctrl_csr_aliasing	4.700s	1.262ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.290s	4.212ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	10.630s	4.185ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.620s	8.729ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.620s	8.729ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.859m	127.224ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			916	920	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.07	96.67	100.00	100.00	98.83	98.33	91.46

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 7.adc_ctrl_filters_both.97904299663278885069068072931293494263667227852524883001816177633655961783516
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.adc_ctrl_filters_both.17460542207844774804863304831398133480329425355533000923862187451340650641148
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.adc_ctrl_stress_all_with_rand_reset.101021388689859947719842581407835726881522057619264335483555898922792569178015
    Line 509, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 127223895402 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 127223895402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [adc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.adc_ctrl_stress_all_with_rand_reset.101132188166463087339997555580380458278643645309394894338653990476234242439419
    Line 554, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132475393217 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 132475393217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9b7e615a7`