ADC_CTRL Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 39.913s 49 50 98.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 5.260s 1.489ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 3.240s 472.456us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.994m 43.546ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 6.240s 817.597us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 3.740s 539.083us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 3.240s 472.456us 20 20 100.00
adc_ctrl_csr_aliasing 6.240s 817.597us 5 5 100.00
V1 TOTAL 104 105 99.05
V2 filters_polled adc_ctrl_filters_polled 24.093m 495.068ms 49 50 98.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 24.978m 498.494ms 49 50 98.00
V2 filters_interrupt adc_ctrl_filters_interrupt 26.187m 492.994ms 49 50 98.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 23.306m 492.111ms 49 50 98.00
V2 filters_wakeup adc_ctrl_filters_wakeup 26.496m 575.101ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 29.517m 615.888ms 49 50 98.00
V2 filters_both adc_ctrl_filters_both 26.918m 553.862ms 49 50 98.00
V2 clock_gating adc_ctrl_clock_gating 25.128m 511.194ms 48 50 96.00
V2 poweron_counter adc_ctrl_poweron_counter 52.546s 48 50 96.00
V2 lowpower_counter adc_ctrl_lowpower_counter 3.262m 46.721ms 49 50 98.00
V2 fsm_reset adc_ctrl_fsm_reset 16.117m 142.888ms 48 50 96.00
V2 stress_all adc_ctrl_stress_all 1.374h 3.096s 49 50 98.00
V2 alert_test adc_ctrl_alert_test 39.940s 49 50 98.00
V2 intr_test adc_ctrl_intr_test 3.340s 512.222us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 5.370s 552.673us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 5.370s 552.673us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 5.260s 1.489ms 5 5 100.00
adc_ctrl_csr_rw 3.240s 472.456us 20 20 100.00
adc_ctrl_csr_aliasing 6.240s 817.597us 5 5 100.00
adc_ctrl_same_csr_outstanding 31.390s 4.371ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 5.260s 1.489ms 5 5 100.00
adc_ctrl_csr_rw 3.240s 472.456us 20 20 100.00
adc_ctrl_csr_aliasing 6.240s 817.597us 5 5 100.00
adc_ctrl_same_csr_outstanding 31.390s 4.371ms 20 20 100.00
V2 TOTAL 725 740 97.97
V2S tl_intg_err adc_ctrl_sec_cm 42.355s 4 5 80.00
adc_ctrl_tl_intg_err 41.460s 8.278ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 41.460s 8.278ms 20 20 100.00
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 2.862m 440.683ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 901 920 97.93

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 16 16 4 25.00
V2S 2 2 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.67 99.07 96.67 100.00 100.00 98.82 98.33 90.79

Failure Buckets

Past Results