ADC_CTRL Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 29.640s 5.569ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.120s 1.143ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 50.259s 18 20 90.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.123m 25.809ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.890s 863.610us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 25.225s 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 50.259s 18 20 90.00
adc_ctrl_csr_aliasing 5.890s 863.610us 5 5 100.00
V1 TOTAL 102 105 97.14
V2 filters_polled adc_ctrl_filters_polled 25.807m 499.911ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 29.183m 502.315ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 24.010m 476.284ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 24.046m 500.667ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 27.112m 530.280ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 36.069m 593.380ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 27.508m 504.095ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 22.917m 531.943ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 26.000s 5.658ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 2.574m 47.309ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 15.983m 144.481ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 1.045h 1.187s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 3.420s 529.838us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 43.096s 37 50 74.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 5.050s 494.365us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 5.050s 494.365us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.120s 1.143ms 5 5 100.00
adc_ctrl_csr_rw 50.259s 18 20 90.00
adc_ctrl_csr_aliasing 5.890s 863.610us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.690s 4.881ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.120s 1.143ms 5 5 100.00
adc_ctrl_csr_rw 50.259s 18 20 90.00
adc_ctrl_csr_aliasing 5.890s 863.610us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.690s 4.881ms 20 20 100.00
V2 TOTAL 727 740 98.24
V2S tl_intg_err adc_ctrl_sec_cm 18.650s 7.721ms 5 5 100.00
adc_ctrl_tl_intg_err 25.509s 19 20 95.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 25.509s 19 20 95.00
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 2.493m 1.032s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 903 920 98.15

Testplan Progress

Items Total Written Passing Progress
V1 6 6 4 66.67
V2 16 16 15 93.75
V2S 2 2 1 50.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.67 99.07 96.67 100.00 100.00 98.82 98.33 90.82

Failure Buckets

Past Results