ADC_CTRL Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 28.600s 5.609ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 6.430s 1.316ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 3.720s 563.689us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 19.570s 20.965ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 8.930s 1.055ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 3.470s 571.123us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 3.720s 563.689us 20 20 100.00
adc_ctrl_csr_aliasing 8.930s 1.055ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 27.202m 486.958ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 26.060m 497.141ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 25.840m 493.341ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 21.777m 500.274ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 27.832m 547.812ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 32.443m 625.561ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 26.094m 570.351ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 27.696m 537.261ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 27.560s 5.604ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 2.926m 41.808ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 15.353m 124.994ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 56.997m 844.489ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 3.730s 464.717us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 3.170s 480.175us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 6.050s 573.969us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 6.050s 573.969us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 6.430s 1.316ms 5 5 100.00
adc_ctrl_csr_rw 3.720s 563.689us 20 20 100.00
adc_ctrl_csr_aliasing 8.930s 1.055ms 5 5 100.00
adc_ctrl_same_csr_outstanding 27.150s 4.832ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 6.430s 1.316ms 5 5 100.00
adc_ctrl_csr_rw 3.720s 563.689us 20 20 100.00
adc_ctrl_csr_aliasing 8.930s 1.055ms 5 5 100.00
adc_ctrl_same_csr_outstanding 27.150s 4.832ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 20.690s 7.926ms 5 5 100.00
adc_ctrl_tl_intg_err 31.270s 8.572ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 31.270s 8.572ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.222m 776.471ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.78 99.07 96.67 100.00 100.00 98.82 98.33 91.54

Past Results